DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet - Page 843

IC H8SX/1543 MCU FLASH 144-LQFP

DF61543J40FPV

Manufacturer Part Number
DF61543J40FPV
Description
IC H8SX/1543 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1500r
Datasheet

Specifications of DF61543J40FPV

Core Processor
H8SX
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, I²C, SCI, SSU
Peripherals
DMA, Motor Control PWM, PWM, WDT
Number Of I /o
95
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561582S000BE - KIT DEV RSK H8SX/1582F
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Oscillator Type
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61543J40FPV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF61543J40FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
23.7.2
Since various characteristics related to the resonator are closely linked to the user's board design,
thorough evaluation is necessary on the user's part, using the resonator connection examples
shown in this section as a reference. As the parameters for the resonator will depend on the
floating capacitance of the resonator and the mounting circuit, the parameters should be
determined in consultation with the resonator manufacturer. The design must ensure that a voltage
exceeding the maximum rating is not applied to the resonator pin.
23.7.3
When using the crystal resonator, place the crystal resonator and its load capacitors as close as
possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the
oscillation circuit as shown in figure 23.6 to prevent induction from interfering with correct
oscillation.
External
clock
Bus master
Notes on Resonator
Notes on Board Design
Figure 23.6 Note on Board Design for Oscillation Circuit
Inhibited
Operating clock
specified in SCKCR
CPU
Figure 23.5 Clock Modification Timing
after the bus cycle completion
C
C
L2
L1
One cycle (worst case)
CPU
Signal A Signal B
Operating clock changed
XTAL
EXTAL
Rev. 3.00 Sep. 24, 2009 Page 795 of 916
This LSI
Section 23 Clock Pulse Generator
CPU
REJ09B0381-0300

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