DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet - Page 72

• Manufacturer Part Number: DF61543J40FPV
• Description: IC H8SX/1543 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1500r

Specifications of DF61543J40FPV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SCI, SSU
• Peripherals: DMA, Motor Control PWM, PWM, WDT
• Number Of I /o: 95
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561582S000BE - KIT DEV RSK H8SX/1582F
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Oscillator Type: -

Section 2 CPU
2.2.3
The data area is extended to 4 Gbytes as compared with that in middle mode.
• Address Space
• Extended Registers (En)
• Instruction Set
• Exception Vector Table and Memory Indirect Branch Addresses
Rev. 3.00 Sep. 24, 2009 Page 24 of 916
REJ09B0381-0300
The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to
16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated.
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.
All instructions and addressing modes can be used.
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower
24 bits are stored. The structure of the exception vector table is shown in figure 2.4.
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch
address. The upper eight bits are reserved and assumed to be H'00.
Advanced Mode
Figure 2.4 Exception Vector Table (Middle and Advanced Modes)
H'00000000
H'00000001
H'00000002
H'00000003
H'00000004
H'00000005
H'00000006
H'00000007
Reset exception vector
Reserved
Reserved
Exception vector table