DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet - Page 668
DF61543J40FPV
Manufacturer Part Number
DF61543J40FPV
Description
IC H8SX/1543 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1500r
Datasheet
1.DF61543J40FPV.pdf
(968 pages)
Specifications of DF61543J40FPV
Core Processor
H8SX
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, I²C, SCI, SSU
Peripherals
DMA, Motor Control PWM, PWM, WDT
Number Of I /o
95
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561582S000BE - KIT DEV RSK H8SX/1582F
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Oscillator Type
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
DF61543J40FPV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF61543J40FPV
Manufacturer:
Renesas Electronics America
Quantity:
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Section 15 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 Sep. 24, 2009 Page 620 of 916
REJ09B0381-0300
[3]
Figure 15.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)
[1]
[2]
No
Note: Hatching boxes represent SSU internal operations.
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
Clear TE and RE in SSER to 0
Write transmit data to SSTDR
Read receive data in SSRDR
TDRE automatically cleared
RDRF automatically cleared
End transmission/reception
Clear TEND in SSSR to 0
transmission/reception?
Read TDRE in SSSR.
Read TEND in SSSR
1-bit period elapsed?
Consecutive data
Initial setting
Read SSSR
ORER = 1?
RDRF = 1?
TDRE = 1?
TEND = 1?
Yes
Start
Yes
No
Yes
Yes
No
Yes
No
No
No
Yes
Error processing
[4]
[5]
[1] Initial setting:
[2] Check the SSU state and write transmit data:
[3] Check the SSU state:
[4] Receive error processing:
[5] Procedure for consecutive data transmission/reception:
Specify the transmit/receive data format.
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE
bit is automatically cleared to 0 and transmission/
reception is started by writing data to SSTDR.
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
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