DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet - Page 488
DF61543J40FPV
Manufacturer Part Number
DF61543J40FPV
Description
IC H8SX/1543 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1500r
Datasheet
1.DF61543J40FPV.pdf
(968 pages)
Specifications of DF61543J40FPV
Core Processor
H8SX
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, I²C, SCI, SSU
Peripherals
DMA, Motor Control PWM, PWM, WDT
Number Of I /o
95
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561582S000BE - KIT DEV RSK H8SX/1582F
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Oscillator Type
-
Available stocks
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Price
Company:
Part Number:
DF61543J40FPV
Manufacturer:
Renesas Electronics America
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Manufacturer:
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Section 12 Serial Communication Interface (SCI)
Rev. 3.00 Sep. 24, 2009 Page 440 of 916
REJ09B0381-0300
Bit
3
PER
Bit Name
Initial
Value
0
R/W
R/(W)* Parity Error
Description
Indicates that a parity error has occurred during reception
in asynchronous mode and the reception ends
abnormally.
[Setting condition]
•
[Clearing condition]
•
When a parity error is detected during reception
Receive data when the parity error occurs is
transferred to RDR, however, the RDRF flag is not
set. Note that when the PER flag is being set to 1, the
subsequent serial reception cannot be performed. In
clocked synchronous mode, serial transmission also
cannot continue.
When 0 is written to PER after reading PER = 1
Even when the RE bit in SCR is cleared, the PER flag
is not affected and retains its previous value.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
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