DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet - Page 33

• Manufacturer Part Number: DF61543J40FPV
• Description: IC H8SX/1543 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1500r

Specifications of DF61543J40FPV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SCI, SSU
• Peripherals: DMA, Motor Control PWM, PWM, WDT
• Number Of I /o: 95
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561582S000BE - KIT DEV RSK H8SX/1582F
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Oscillator Type: -

Figure 9.26 Example of Phase Counting Mode 2 Operation ...................................................... 371
Figure 9.27 Example of Phase Counting Mode 3 Operation ...................................................... 372
Figure 9.28 Example of Phase Counting Mode 4 Operation ...................................................... 373
Figure 9.29 Phase Counting Mode Application Example .......................................................... 375
Figure 9.30 Count Timing in Internal Clock Operation ............................................................. 379
Figure 9.31 Count Timing in External Clock Operation ............................................................ 379
Figure 9.32 Output Compare Output Timing ............................................................................. 380
Figure 9.33 Input Capture Input Signal Timing ......................................................................... 380
Figure 9.34 Counter Clear Timing (Compare Match) ................................................................ 381
Figure 9.35 Counter Clear Timing (Input Capture) .................................................................... 381
Figure 9.36 Buffer Operation Timing (Compare Match) ........................................................... 382
Figure 9.37 Buffer Operation Timing (Input Capture) ............................................................... 382
Figure 9.38 TGI Interrupt Timing (Compare Match) ................................................................. 383
Figure 9.39 TGI Interrupt Timing (Input Capture)..................................................................... 383
Figure 9.40 TCIV Interrupt Setting Timing................................................................................ 384
Figure 9.41 TCIU Interrupt Setting Timing................................................................................ 384
Figure 9.42 Timing for Status Flag Clearing by CPU ................................................................ 385
Figure 9.43 Timing for Status Flag Clearing by DMAC Activation (1)..................................... 386
Figure 9.44 Timing for Status Flag Clearing by DMAC Activation (2)..................................... 386
Figure 9.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .................. 387
Figure 9.46 Conflict between TCNT Write and Clear Operations ............................................. 388
Figure 9.47 Conflict between TCNT Write and Increment Operations...................................... 389
Figure 9.48 Conflict between TGR Write and Compare Match ................................................. 389
Figure 9.49 Conflict between Buffer Register Write and Compare Match ................................ 390
Figure 9.50 Conflict between TGR Read and Input Capture...................................................... 391
Figure 9.51 Conflict between TGR Write and Input Capture..................................................... 391
Figure 9.52 Conflict between Buffer Register Write and Input Capture .................................... 392
Figure 9.53 Conflict between Overflow and Counter Clearing .................................................. 393
Figure 9.54 Conflict between TCNT Write and Overflow ......................................................... 394
Section 10 Watchdog Timer (WDT)
Figure 10.1 Block Diagram of WDT.......................................................................................... 395
Figure 10.2 Operation in Watchdog Timer Mode ...................................................................... 400
Figure 10.3 Operation in Interval Timer Mode .......................................................................... 401
Figure 10.4 Writing to TCNT, TCSR, and RSTCSR ................................................................. 402
Figure 10.5 Conflict between TCNT Write and Increment ........................................................ 403
Section 11 Watch Timer (WAT)
Figure 11.1 Block Diagram of WAT.......................................................................................... 405
Figure 11.2 Operation in Compare Match Timer Mode ............................................................. 412
Rev. 3.00 Sep. 24, 2009 Page xxxi of xlvi
REJ09B0381-0300