DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet - Page 30

• Manufacturer Part Number: DF61543J40FPV
• Description: IC H8SX/1543 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1500r

Specifications of DF61543J40FPV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SCI, SSU
• Peripherals: DMA, Motor Control PWM, PWM, WDT
• Number Of I /o: 95
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561582S000BE - KIT DEV RSK H8SX/1582F
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Oscillator Type: -

Section 5 Interrupt Controller
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Figure 5.7
Section 6 Bus Controller (BSC)
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10 Access Sizes and Data Alignment Control for 16-Bit Access Space
Figure 6.11 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address) .......... 163
Figure 6.12 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address)............ 164
Figure 6.13 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address) ......... 165
Figure 6.14 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address) .......... 166
Figure 6.15 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address) .......... 167
Figure 6.16 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address) ......... 168
Figure 6.17 Example of Wait Cycle Insertion Timing ............................................................... 169
Figure 6.18 Example of Read Strobe Timing............................................................................. 170
Figure 6.19 DACK Signal Output Timing ................................................................................. 171
Figure 6.20 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) ............ 174
Figure 6.21 Example of Idle Cycle Operation (Write after Read).............................................. 175
Figure 6.22 Example of Idle Cycle Operation (Read after Write).............................................. 176
Figure 6.23 Example of Idle Cycle Operation (Write after Single Address Transfer Write) ..... 177
Figure 6.24 Idle Cycle Insertion Example.................................................................................. 178
Figure 6.25 Example of Timing when Write Data Buffer Function Is Used.............................. 182
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Block Diagram of Interrupt Controller...................................................................... 94
Block Diagram of Interrupts IRQn.......................................................................... 111
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control
Mode 0 .................................................................................................................... 118
Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control
Mode 2 .................................................................................................................... 120
Interrupt Exception Handling.................................................................................. 121
Block Diagram of DMAC and Interrupt Controller ................................................ 124
Conflict between Interrupt Generation and Disabling............................................. 128
Block Diagram of Bus Controller ........................................................................... 132
Read Strobe Negation Timing (Example of 3-State Access Space)........................ 142
Internal Bus Configuration...................................................................................... 148
System Clock: External Bus Clock = 4:1, External 2-State Access ........................ 150
System Clock: External Bus Clock = 2:1, External 3-State Access ........................ 151
Address Space Area Division.................................................................................. 154
Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian).. 159
Access Sizes and Data Alignment Control for 8-Bit Access Space
(Little Endian) ......................................................................................................... 159
Access Sizes and Data Alignment Control for 16-Bit Access Space (Big Endian). 160
(Little Endian) ......................................................................................................... 161