DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet - Page 29

IC H8SX/1543 MCU FLASH 144-LQFP

DF61543J40FPV

Manufacturer Part Number
DF61543J40FPV
Description
IC H8SX/1543 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1500r
Datasheet

Specifications of DF61543J40FPV

Core Processor
H8SX
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, I²C, SCI, SSU
Peripherals
DMA, Motor Control PWM, PWM, WDT
Number Of I /o
95
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
R0K561582S000BE - KIT DEV RSK H8SX/1582F
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Oscillator Type
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61543J40FPV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF61543J40FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 1 Overview
Figure 1.1
Figure 1.2
Section 2 CPU
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8
Figure 2.9
Figure 2.10 Usage of General Registers ....................................................................................... 29
Figure 2.11 Stack.......................................................................................................................... 30
Figure 2.12 General Register Data Formats ................................................................................. 34
Figure 2.13 Memory Data Formats .............................................................................................. 35
Figure 2.14 Instruction Formats ................................................................................................... 53
Figure 2.15 Branch Address Specification in Memory Indirect Mode......................................... 60
Figure 2.16 State Transitions........................................................................................................ 65
Section 3 MCU Operating Modes
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Section 4 Exception Handling
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Memory Map............................................................................................................. 27
CPU Registers ........................................................................................................... 28
Block Diagram of H8SX/1544 .................................................................................... 2
Pin Assignments of H8SX/1544.................................................................................. 3
CPU Operating Modes .............................................................................................. 21
Exception Vector Table (Normal Mode)................................................................... 22
Stack Structure (Normal Mode) ................................................................................ 22
Exception Vector Table (Middle and Advanced Modes) .......................................... 24
Stack Structure (Middle and Advanced Modes)........................................................ 25
Exception Vector Table (Maximum Modes)............................................................. 26
Stack Structure (Maximum Mode)............................................................................ 26
H8SX/1544 Address Map (1).................................................................................... 75
H8SX/1544 Address Map (2).................................................................................... 76
H8SX/1543 Address Map (1).................................................................................... 77
H8SX/1543 Address Map (2).................................................................................... 78
Reset Sequence (On-Chip ROM Enabled Advanced Mode)..................................... 83
Reset Sequence
Stack Status after Exception Handling ...................................................................... 91
Operation when SP Value Is Odd.............................................................................. 92
(16-Bit External Access in On-Chip ROM Disabled Advanced Mode) ................... 84
Figures
Rev. 3.00 Sep. 24, 2009 Page xxvii of xlvi
REJ09B0381-0300

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