DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet - Page 145

• Manufacturer Part Number: DF61543J40FPV
• Description: IC H8SX/1543 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1500r

Specifications of DF61543J40FPV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SCI, SSU
• Peripherals: DMA, Motor Control PWM, PWM, WDT
• Number Of I /o: 95
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561582S000BE - KIT DEV RSK H8SX/1582F
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Oscillator Type: -

5.3.2
CPUPCR sets whether or not the CPU has priority over the DMAC. The interrupt exception
handling by the CPU can be given priority over that of the DMAC transfer. The priority level of
the DMAC is set by the DMAC control register for each channel.
Bit
Bit Name
Initial Value
R/W
Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.
Bit
7
6 to 4
3
Bit Name
CPUPCE
⎯
IPSETE
CPU Priority Control Register (CPUPCR)
CPUPCE
R/W
7
0
Initial
Value
0
All 0
0
R/W
—
6
0
R/W
R/W
R
R/W
R/W
—
5
0
Description
CPU Priority Control Enable
Controls the CPU priority control function. Setting this bit
to 1 enables the CPU priority control over the DMAC.
0: CPU always has the lowest priority
1: CPU priority control enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
Interrupt Priority Set Enable
Controls the function which automatically assigns the
interrupt priority level of the CPU. Setting this bit to 1
automatically sets bits CPUP2 to CPUP0 by the CPU
interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR).
0: Bits CPUP2 to CPUP0 are not updated automatically
1: The interrupt mask bit value is reflected in bits CPUP2
to CPUP0
R/W
—
4
0
IPSETE
R/W
3
0
Rev. 3.00 Sep. 24, 2009 Page 97 of 916
CPUP2
R/(W)*
2
0
Section 5 Interrupt Controller
CPUP1
R/(W)*
1
0
REJ09B0381-0300
CPUP0
R/(W)*
0
0