DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet
DF61543J40FPV
Specifications of DF61543J40FPV
Available stocks
Related parts for DF61543J40FPV
DF61543J40FPV Summary of contents
Page 1
To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
Page 2
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
Page 3
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8SX/1544 Group 32 Hardware Manual Renesas 32-Bit ...
Page 4
This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
Page 5
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
Page 6
Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules ...
Page 7
The H8SX/1544 Group is a single-chip microcomputer made up of the high-speed internal 32-bit H8SX CPU as its core, and the peripheral functions required to configure a system. The H8SX CPU is upward compatible with the H8/300, H8/300H, and H8S ...
Page 8
H8SX/1544 Group manuals: Document Title H8SX/1544 Group Hardware Manual H8SX Family Software Manual Rev. 3.00 Sep. 24, 2009 Page vi of xlvi REJ09B0381-0300 Document No. This manual REJ09B0102 ...
Page 9
Main Revisions for This Edition Item Page 14.6 Application Note 571 14.6.1 Configuration of RCAN-ET (1) After a reset request Figure 14.6 Reset Sequence 15.4.6 SCS Pin Control 621 and Conflict Error Figure 15.11 Conflict Error Detection Timing (After Transfer ...
Page 10
Item Page 26.2 DC 879 Characteristics Table 26.2 DC Characteristics (2) 26.3.3 Bus Timing 888 Table 26.6 Bus Timing (1) 26.3.4 DMAC Timing 892 Table 26.7 DMAC Timing All trademarks and registered trademarks are the property of their respective owners. ...
Page 11
Section 1 Overview..............................................................................................1 1.1 Features.................................................................................................................................. 1 1.2 Block Diagram ....................................................................................................................... 2 1.3 Pin Assignments..................................................................................................................... 3 1.3.1 Pin Assignments ....................................................................................................... 3 1.3.2 Pin Configuration in Each Operating Mode.............................................................. 4 1.3.3 Pin Functions ............................................................................................................ 9 Section 2 CPU....................................................................................................19 2.1 Features................................................................................................................................ 19 2.2 ...
Page 12
Register Indirect with Displacement⎯@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn) .................................................................................................... 55 2.8.4 Index Register Indirect with Displacement⎯@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 56 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement⎯@ERn+, @−ERn, @+ERn, or @ERn− ................................ ...
Page 13
Address Error ....................................................................................................................... 86 4.5.1 Address Error Source.............................................................................................. 86 4.5.2 Address Error Exception Handling ......................................................................... 87 4.6 Interrupts.............................................................................................................................. 88 4.6.1 Interrupt Sources..................................................................................................... 88 4.6.2 Interrupt Exception Handling ................................................................................. 88 4.7 Instruction Exception Handling ........................................................................................... 89 4.7.1 Trap Instruction....................................................................................................... 89 ...
Page 14
Interrupts during Execution of MOVMD and MOVSD Instructions.................... 129 5.8.6 Interrupt Flags of Peripheral Modules .................................................................. 130 Section 6 Bus Controller (BSC) ...................................................................... 131 6.1 Features.............................................................................................................................. 131 6.2 Register Descriptions......................................................................................................... 133 6.2.1 Bus Width Control Register (ABWCR) ............................................................... 134 ...
Page 15
Bus Controller Operation in Reset ..................................................................................... 186 6.12 Usage Notes ....................................................................................................................... 186 Section 7 DMA Controller (DMAC) ...............................................................187 7.1 Features.............................................................................................................................. 187 7.2 Input/Output Pins ............................................................................................................... 189 7.3 Register Descriptions ......................................................................................................... 190 7.3.1 DMA Source Address Register (DSAR) .............................................................. 191 ...
Page 16
Input Buffer Control Register (PnICR and K) .... 267 8.1.5 Pull-Up MOS Control Register (PnPCR and H to K)...................... 268 8.1.6 Open-Drain ...
Page 17
Synchronous Operation......................................................................................... 355 9.4.3 Buffer Operation ................................................................................................... 357 9.4.4 Cascaded Operation .............................................................................................. 361 9.4.5 PWM Modes ......................................................................................................... 363 9.4.6 Phase Counting Mode........................................................................................... 368 9.5 Interrupt Sources................................................................................................................ 376 9.6 DMAC Activation.............................................................................................................. 378 9.7 A/D Converter Activation.................................................................................................. 378 9.8 Operation Timing............................................................................................................... ...
Page 18
Changing Values of Bits CKS2 to CKS0.............................................................. 403 10.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 403 10.5.5 Transition to Watchdog Timer Mode or Software Standby Mode........................ 404 Section 11 Watch Timer (WAT) ....................................................................... 405 11.1 Features.............................................................................................................................. ...
Page 19
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................................................... 450 12.4.3 Clock..................................................................................................................... 451 12.4.4 SCI Initialization (Asynchronous Mode) .............................................................. 452 12.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 453 12.4.6 Serial Data Reception (Asynchronous Mode)....................................................... 455 12.5 Multiprocessor ...
Page 20
Section Bus Interface 2 (IIC2)................................................................ 491 13.1 Features.............................................................................................................................. 491 13.2 Input/Output Pins............................................................................................................... 493 13.3 Register Descriptions......................................................................................................... 494 2 13.3 Bus Control Register A (ICCRA) ................................................................... 495 2 13.3 Bus Control Register B ...
Page 21
Message Data Fields ............................................................................................. 536 14.4 RCAN-ET Control Registers ............................................................................................. 537 14.4.1 Master Control Register (MCR) ........................................................................... 537 14.4.2 General Status Register (GSR) ............................................................................. 543 14.4.3 Bit Configuration Registers 0 and 1 (BCR0 and BCR1) ...................................... 546 14.4.4 Interrupt ...
Page 22
SS Mode Register (SSMR) ................................................................................... 597 15.3.4 SS Enable Register (SSER) .................................................................................. 598 15.3.5 SS Status Register (SSSR).................................................................................... 599 15.3.6 SS Control Register 2 (SSCR2) ............................................................................ 602 15.3.7 SS Transmit Data Registers (SSTDR0 to SSTDR3)................................... 604 ...
Page 23
Section 17 D/A Converter..................................................................................649 17.1 Features.............................................................................................................................. 649 17.2 Input/Output Pins ............................................................................................................... 650 17.3 Register Descriptions ......................................................................................................... 650 17.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................. 650 17.3.2 D/A Control Register 01 (DACR01) .................................................................... 651 17.4 Operation ........................................................................................................................... 653 ...
Page 24
PWM Counter (PWCNT) ..................................................................................... 678 19.3.4 PWM Cycle Register (PWCYR) .......................................................................... 678 19.3.5 PWM Duty Registers (PWDTR0 to PWDTR3) ......................................... 679 19.3.6 PWM Buffer Registers (PWBFR0 to PWBFR3) ........................................ 681 19.4 Operation ........................................................................................................................... ...
Page 25
Register Descriptions ......................................................................................................... 711 22.6.1 Programming/Erasing Interface Registers ............................................................ 712 22.6.2 Programming/Erasing Interface Parameters ......................................................... 718 22.6.3 RAM Emulation Register (RAMER).................................................................... 732 22.7 On-Board Programming Mode .......................................................................................... 733 22.7.1 Boot Mode ............................................................................................................ 733 22.7.2 User Program Mode.............................................................................................. 737 22.7.3 ...
Page 26
Multi-Clock Function of Main Clock ................................................................................ 807 24.4 Sub-Clock .......................................................................................................................... 808 24.5 Sleep Mode ........................................................................................................................ 808 24.5.1 Transition to Sleep Mode...................................................................................... 808 24.5.2 Clearing Sleep Mode ............................................................................................ 809 24.6 Software Standby Mode..................................................................................................... 809 24.6.1 Transition to Software Standby Mode ...
Page 27
A/D Conversion Characteristics ........................................................................... 903 26.3.7 D/A Conversion Characteristics ........................................................................... 903 26.3.8 Flash Memory Characteristics .............................................................................. 904 Appendix .........................................................................................................905 A. Port States in Each Pin State .............................................................................................. 905 B. Product Lineup................................................................................................................... 907 C. Package Dimensions .......................................................................................................... 908 Index .........................................................................................................909 ...
Page 28
Rev. 3.00 Sep. 24, 2009 Page xxvi of xlvi REJ09B0381-0300 ...
Page 29
Section 1 Overview Figure 1.1 Block Diagram of H8SX/1544 .................................................................................... 2 Figure 1.2 Pin Assignments of H8SX/1544.................................................................................. 3 Section 2 CPU Figure 2.1 CPU Operating Modes .............................................................................................. 21 Figure 2.2 Exception Vector Table (Normal Mode)................................................................... 22 Figure 2.3 Stack Structure ...
Page 30
Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller...................................................................... 94 Figure 5.2 Block Diagram of Interrupts IRQn.......................................................................... 111 Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 .................................................................................................................... 118 Figure 5.4 Flowchart of ...
Page 31
Figure 6.26 Example of Timing when Peripheral Module Write Data Buffer Function Is Used ........................................................................................................................ 183 Section 7 DMA Controller (DMAC) Figure 7.1 Block Diagram of DMAC ....................................................................................... 188 Figure 7.2 Example of Signal Timing in Dual Address Mode ................................................. ...
Page 32
Figure 7.30 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level ....................................................................................................................... 242 Figure 7.31 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level .... 243 Figure 7.32 Example of Transfer in Normal Transfer ...
Page 33
Figure 9.26 Example of Phase Counting Mode 2 Operation ...................................................... 371 Figure 9.27 Example of Phase Counting Mode 3 Operation ...................................................... 372 Figure 9.28 Example of Phase Counting Mode 4 Operation ...................................................... 373 Figure 9.29 Phase Counting Mode Application Example ...
Page 34
Figure 11.3 Operation in Interval Timer Mode .......................................................................... 414 Figure 11.4 Conflict between WTCNT Write and Increment .................................................... 416 Section 12 Serial Communication Interface (SCI) Figure 12.1 Block Diagram of SCI............................................................................................. 420 Figure 12.2 Data Format in Asynchronous Communication (Example ...
Page 35
Figure 12.28 Sample Transmission Flowchart ............................................................................. 479 Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode.............................................. 480 Figure 12.30 Sample Reception Flowchart................................................................................... 481 Figure 12.31 Clock Output Fixing Timing ................................................................................... 481 Figure 12.32 Clock Stop and Restart Procedure........................................................................... 482 Figure ...
Page 36
Figure 14.7 Halt Mode/Sleep Mode ........................................................................................... 573 Figure 14.8 Halt Mode/Sleep Mode ........................................................................................... 574 Figure 14.9 Transmission Request ............................................................................................. 577 Figure 14.10 Internal Arbitration for Transmission...................................................................... 578 Figure 14.11 Message receive sequence....................................................................................... 579 Figure 14.12 Change ID of Receive Box ...
Page 37
Figure 15.13 Example of Transmission Operation (Clock Synchronous Communication Mode) .......................................................... 623 Figure 15.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode) .......................................................... 624 Figure 15.15 Example of Reception Operation (Clock Synchronous Communication Mode)..... 625 Figure 15.16 Flowchart Example ...
Page 38
Section 19 16-Bit PWM Figure 19.1 Block Diagram of PWM ......................................................................................... 672 Figure 19.2 Cycle Register Compare Match .............................................................................. 678 Figure 19.3 Operation in 16-Bit PWM Mode............................................................................. 683 Figure 19.4 Operation in 10-Bit Stepping Motor Mode ............................................................. 684 Figure 19.5 ...
Page 39
Section 23 Clock Pulse Generator Figure 23.1 Block Diagram of Clock Pulse Generator ............................................................... 785 Figure 23.2 Connection of Crystal Resonator (Example)........................................................... 791 Figure 23.3 Crystal Resonator Equivalent Circuit...................................................................... 791 Figure 23.4 External Clock Input (Examples) ............................................................................ 792 Figure 23.5 ...
Page 40
Figure 26.25 SSU Timing (Master, CPHS = 0)............................................................................ 901 Figure 26.26 SSU Timing (Slave, CPHS = 1) .............................................................................. 902 Figure 26.27 SSU Timing (Slave, CPHS = 0) .............................................................................. 902 Appendix Figure C.1 Package Dimensions (FP-144L).............................................................................. 908 Rev. 3.00 Sep. 24, ...
Page 41
Section 1 Overview Table 1.1 Pin Configuration in Each Operating Mode ................................................................ 4 Table 1.2 Pin Functions............................................................................................................... 9 Section 2 CPU Table 2.1 Instruction Classification........................................................................................... 36 Table 2.2 Combinations of Instructions and Addressing Modes (1) ......................................... 38 Table 2.2 Combinations ...
Page 42
Section 5 Interrupt Controller Table 5.1 Pin Configuration ...................................................................................................... 95 Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority .......................... 112 Table 5.3 Interrupt Control Modes.......................................................................................... 117 Table 5.4 Interrupt Response Times ....................................................................................... 122 Table 5.5 Number of Execution ...
Page 43
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.1 TPU Functions ........................................................................................................ 308 Table 9.2 Pin Configuration .................................................................................................... 311 Table 9.3 CCLR2 to CCLR0 (Channels 0 and 3).................................................................... 315 Table 9.4 CCLR2 to CCLR0 (Channels and 5)........................................................... ...
Page 44
Section 10 Watchdog Timer (WDT) Table 10.1 WDT Interrupt Source............................................................................................. 401 Section 12 Serial Communication Interface (SCI) Table 12.1 Pin Configuration .................................................................................................... 421 Table 12.2 Relationships between N Setting in BRR and Bit Rate B ....................................... 443 Table 12.3 Examples ...
Page 45
Section 15 Synchronous Serial Communication Unit (SSU) Table 15.1 Pin Configuration .................................................................................................... 591 Table 15.2 Communication Modes and Pin States of SSI and SSO Pins.................................. 609 Table 15.3 Communication Modes and Pin States of SSCK Pin .............................................. 610 Communication Modes ...
Page 46
Table 22.5 On-Board Programming Mode Setting ................................................................... 733 Table 22.6 System Clock Frequency for Automatic-Bit-Rate Adjustment ............................... 734 Table 22.7 Executable Memory MAT ...................................................................................... 748 Table 22.8 Usable Area for Programming in User Program Mode........................................... 748 Table 22.9 Usable Area ...
Page 47
Appendix Table A.1 Port States in Each Pin State ................................................................................... 905 Rev. 3.00 Sep. 24, 2009 Page xlv of xlvi REJ09B0381-0300 ...
Page 48
Rev. 3.00 Sep. 24, 2009 Page xlvi of xlvi REJ09B0381-0300 ...
Page 49
Features • 32-bit high-speed H8SX CPU Upward compatible at object level with the H8/300 CPU, H8/300H CPU, and H8S CPU Sixteen 16-bit general registers 87 basic instructions • Extensive peripheral functions DMA controller (DMAC) 16-bit timer pulse unit (TPU) ...
Page 50
Section 1 Overview • Small package Package Code LQFP-144 FP-144L 1.2 Block Diagram RAM ROM H8SX CPU Clock pulse generator Legend: CPU: Central processing unit DMAC: DMA controller BSC: Bus controller WDT: Watchdog timer WAT: Watch timer TPU: 16-bit timer ...
Page 51
Pin Assignments 1.3.1 Pin Assignments 109 P40/AN12 110 P41/AN13 111 P42/AN14 112 P43/AN15 113 P44/AN8 114 P45/AN9 115 P46/AN10 116 P47/AN11 117 AVcc1 118 Vref 119 AVcc0 120 AVss 121 P50/AN0 122 P51/AN1 123 P52/AN2 124 P53/AN3 125 P54/AN4 ...
Page 52
Section 1 Overview 1.3.2 Pin Configuration in Each Operating Mode Table 1.1 Pin Configuration in Each Operating Mode Abbreviation in Pin No. Mode 2, Mode 6, and Mode 7 1 PI4/D12 2 PI5/D13 3 PI6/D14 4 PI7/D15 5 Vcc 6 ...
Page 53
Abbreviation in Pin No. Mode 2, Mode 6, and Mode 7 30 PWMVss 31 PF4/A20/PWM0_1 32 PF5/A21/TxD5/PWM1_1 33 PF6/A22/RxD5/PWM2_1 34 PF7/A23/SCK5/PWM3_1 35 PJ0/PWM1A 36 PJ1/PWM1B 37 PJ2/PWM1C 38 PJ3/PWM1D 39 PWMVcc 40 PWMVss 41 PJ4/PWM1E 42 PJ5/PWM1F 43 PJ6/PWM1G 44 ...
Page 54
Section 1 Overview Abbreviation in Pin No. Mode 2, Mode 6, and Mode 7 59 P14/SDA1/IRQ4-A/DREQ1_A 60 P15/SCL1/IRQ5-A/TEND1_A 61 P16/SDA0/IRQ6-A/DACK1_A 62 P17/SCL0/IRQ7-A/ADTRG1 63 PA0/TDO/PWM0_2 64 PA1/TDI/PWM1_2 65 PA2/TCK/PWM2_2 66 P63/IRQ11-B/PWM3_2/TMS/DREQ3_B 67 P64/IRQ12-B/CRx_0/TEND3_B 68 P65/IRQ13-B/CTx_0/DACK3_B 69 P66/IRQ14-B/CRx_1 70 P67/IRQ15-B/CTx_1 71 Vcc ...
Page 55
Abbreviation in Pin No. Mode 2, Mode 6, and Mode 7 89 P26/TIOCA5 90 P27/TIOCB5 91 NMI 92 EMLE Vss 95 XTAL 96 EXTAL 97 Vss 98 Vcc RES 99 100 P37/TIOCB2/TCLKD_A/SGOUT_3 101 P36/TIOCA2/SGOUT_2 102 P35/TIOCB1/TCLKC_A/SGOUT_1 ...
Page 56
Section 1 Overview Abbreviation in Pin No. Mode 2, Mode 6, and Mode 7 119 AVcc0 120 AVss 121 P50/AN0 122 P51/AN1 123 P52/AN2 124 P53/AN3 125 P54/AN4 126 P55/AN5 127 P56/AN6/DA0 128 P57/AN7/DA1 129 MD1 130 MD0 131 PH0/D0 ...
Page 57
Pin Functions Table 1.2 Pin Functions Classification Abbreviation Power supply Clock XTAL EXTAL Bφ Operating MD2 mode control MD1 MD0 RES System control STBY EMLE Address bus A23 to A20 A19 to A8 ...
Page 58
Section 1 Overview Classification Abbreviation RD Bus control AS LHWR LLWR Interrupts NMI IRQ15-B IRQ14-B IRQ13-B IRQ12-B IRQ11-B IRQ10-B IRQ9-B IRQ8-B IRQ7-A IRQ6-A IRQ5-A IRQ4-A IRQ3-A IRQ2-A IRQ1-A IRQ0-A TRST On-chip emulator TMS TDO TDI TCK Rev. 3.00 Sep. 24, ...
Page 59
Classification Abbreviation DREQ0_A DMA controller (DMAC) DREQ1_A DREQ2_B DREQ3_B DACK0_A DACK1_A DACK2_B DACK3_B TEND0_A TEND1_A TEND2_B TEND3_B 16-bit timer TCLKA-A pulse unit TCLKB-A (TPU) TCLKC-A (unit 0) TCLKD-A TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 ...
Page 60
Section 1 Overview Classification Abbreviation Motor control PWM1A to PWM timer PWM1H PWM2A to PWM2H 16-bit PWM PWM0_0 to PWM3_0 PWM0_1 to PWM3_1 PWM0_2 to PWM3_2 PWM power PWMVcc supply PWMVss Serial TxD0 communication TxD2 interface (SCI) TxD4 TxD5 RxD0 ...
Page 61
Classification Abbreviation Synchronous SSO_1 serial SSO_0 communication SSI_1 unit (SSU) SSI_0 SSCK_1 SSCK_0 SCS_1 SCS_0 Sound SGOUT3 to generator SGOUT0 (SDG) A/D converter AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 ADTRG1 ...
Page 62
Section 1 Overview Classification Abbreviation A/D converter Vref D/A converter DA1 DA0 I/O port P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 Rev. 3.00 ...
Page 63
Classification Abbreviation I/O port P37 P36 P35 P34 P33 P32 P31 P30 P47 P46 P45 P44 P43 P42 P41 P40 P57 P56 P55 P54 P53 P52 P51 P50 P67 P66 P65 P64 P63 P62 P61 P60 Pin Number I/O Description ...
Page 64
Section 1 Overview Classification Abbreviation I/O port PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Rev. ...
Page 65
Classification Abbreviation I/O port PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 Pin Number I/O Description ...
Page 66
Section 1 Overview Rev. 3.00 Sep. 24, 2009 Page 18 of 916 REJ09B0381-0300 ...
Page 67
The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward- compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ...
Page 68
Section 2 CPU • Two base registers ⎯ Vector base register ⎯ Short address base register • 4-Gbyte address space ⎯ Program: 4 Gbytes ⎯ Data: 4 Gbytes • High-speed operation ⎯ All frequently-used instructions executed in one or two ...
Page 69
CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced, and maximum modes. For details on mode settings, see section 3.1, Operating Mode Selection. CPU operating modes 2.2.1 Normal Mode The exception vector table and stack ...
Page 70
Section 2 CPU • Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the ...
Page 71
Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. Note: Middle mode is not supported in this LSI. • Address Space The maximum address space of 16 Mbytes ...
Page 72
Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas ...
Page 73
Stack Structure The stack structure subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. SP Reserved (a) ...
Page 74
Section 2 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute ...
Page 75
Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch ...
Page 76
Section 2 CPU 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register ...
Page 77
General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...
Page 78
Section 2 CPU SP (ER7) 2.5.2 Program Counter (PC 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word multiple ...
Page 79
Initial Bit Bit Name Value 5 H Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R/W R/W Description Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, ...
Page 80
Section 2 CPU 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ...
Page 81
Multiply-Accumulate Register (MAC) MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are sign extended. ...
Page 82
Section 2 CPU 1-bit data 1-bit data 4-bit BCD data 4-bit BCD data Byte data Byte data Word data Word data Longword data 15 MSB 31 MSB Legend: ERn: En: Rn: RnH: Figure 2.12 General Register Data Formats Rev. 3.00 ...
Page 83
Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword ...
Page 84
Section 2 CPU 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in ...
Page 85
Function Instructions Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC 5 Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC Legend: B: Byte size W: Word size L: Longword size Notes: 1. ...
Page 86
Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Classifi- cation Instruction Size Data transfer MOV ...
Page 87
Classifi- cation Instruction Size Arithmetic MULXU, DIVXU B/W operations MULU, DIVU W/L MULXS, DIVXS B/W MULS, DIVS W/L NEG B W/L EXTU, EXTS W/L TAS B ⎯ MAC ⎯ CLRMAC ⎯ LDMAC ⎯ STMAC Logic AND, OR, XOR B operations ...
Page 88
Section 2 CPU Classifi- cation Instruction Size Bit BFLD B manipu- BFST B lation Branch BRA/BS BRA/BC* BSR/BS BSR/BC* System LDC (CCR, EXR) B/W* control LDC (VBR, SBR) L STC (CCR, EXR) B/W* STC (VBR, SBR) ...
Page 89
Table 2.2 Combinations of Instructions and Addressing Modes (2) Classifi- cation Instruction Size ⎯ Branch BRA/BS, BRA/BC ⎯ BSR/BS, BSR/BC ⎯ Bcc ⎯ BRA ⎯ BRA/S ⎯ JMP ⎯ BSR ⎯ JSR RTS, RTS/L ⎯ ⎯ System TRAPA control RTE, ...
Page 90
Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd ...
Page 91
Table 2.4 Data Transfer Instructions Instruction Size Function #IMM → (EAd), (EAs) → (EAd) MOV B/W/L Transfers data between immediate data, general registers, and memory. (EAs) → Rd MOVFPE → (EAs) MOVTPE* B @SP+ → Rn POP W/L ...
Page 92
Section 2 CPU Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B B Transfers a data block. EEPMOV.W Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of ...
Page 93
Table 2.6 Arithmetic Operation Instructions Instruction Size Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) ADD B/W/L SUB Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted ...
Page 94
Section 2 CPU Instruction Size Function Rd ÷ Rs → Rd DIVXU B/W Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder bits ÷ 16 bits ...
Page 95
Instruction Size Function ⎯ Rs → MAC LDMAC Loads data from a general register to MAC. ⎯ MAC → Rd STMAC Stores data from MAC to a general register. Table 2.7 Logic Operation Instructions Instruction Size Function (EAd) ∧ #IMM ...
Page 96
Section 2 CPU Table 2.8 Shift Operation Instructions Instruction Size Function (EAd) (shift) → (EAd) SHLL B/W/L SHLR Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or ...
Page 97
Table 2.9 Bit Manipulation Instructions Instruction Size Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified by 3-bit immediate ...
Page 98
Section 2 CPU Instruction Size Function C ∨ [~ (<bit-No.> of <EAd>)] → C BIOR B ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores ...
Page 99
Instruction Size Function ∼ Z → (<bit-No.> of <EAd>) BISTZ B Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data. (EAs) ...
Page 100
Section 2 CPU Table 2.11 System Control Instructions Instruction Size Function ⎯ TRAPA Starts trap-instruction exception handling. ⎯ RTE Returns from an exception-handling routine. ⎯ RTE/L Returns from an exception-handling routine, restoring data from the stack to multiple general registers. ...
Page 101
Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.14 ...
Page 102
Section 2 CPU 2.8 Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or ...
Page 103
Register Direct⎯Rn The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit ...
Page 104
Section 2 CPU 2.8.4 Index Register Indirect with Displacement⎯@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L) The operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- ...
Page 105
Register indirect with post-decrement⎯@ERn− (4) The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the ...
Page 106
Section 2 CPU 2.8.6 Absolute Address⎯@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is the contents of a memory location which is pointed absolute address included in the instruction code. There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit ...
Page 107
Immediate⎯#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate ...
Page 108
Section 2 CPU 2.8.10 Memory Indirect⎯@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the content of a memory location pointed 8-bit absolute address in ...
Page 109
Extended Memory Indirect⎯@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of ...
Page 110
Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. Addressing Mode and Instruction Format 1 Immediate op IMM Register direct Register indirect Register indirect with 16-bit displacement ...
Page 111
Table 2.15 Effective Address Calculation for Branch Instructions No. Addressing Mode and Instruction Format Register indirect Program-counter relative with 8-bit displacement 2 op disp Program-counter relative with 16-bit displacement op disp Program-counter relative with index register 3 ...
Page 112
Section 2 CPU 2.9 Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. • Reset state In this state ...
Page 113
RES = high Exception-handling state Request for exception End of exception handling handling Program execution state A transition to the reset state occurs whenever the RES signal goes low. Note transition can also be made to the reset ...
Page 114
Section 2 CPU Rev. 3.00 Sep. 24, 2009 Page 66 of 916 REJ09B0381-0300 ...
Page 115
Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has five operating modes (modes and 7). The operating mode is selected by the setting of mode pins (MD2 to MD0). Table 3.1 lists MCU ...
Page 116
Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode setting. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR indicates the current operating mode. When ...
Page 117
Bit Bit Name Initial Value R/W ⎯ ⎯ ⎯ ⎯ ⎯ 3 Undefined* ⎯ 2 Undefined* ⎯ 1 Undefined* ⎯ 0 Undefined* Note: * Determined by pins MD2 to MD0. Table 3.2 ...
Page 118
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, and enables or disables the on-chip RAM. Bit 15 14 ⎯ ⎯ Bit Name ...
Page 119
Initial Bit Bit Name Value ⎯ EXPE Undefined 8 RAME 1 ⎯ All 0 ⎯ All 1 Notes: 1. For details on instruction fetch mode, see section 2.3, Instruction Fetch. 2. The ...
Page 120
Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 2 This is the boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash ...
Page 121
Mode 6 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is enabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access ...
Page 122
Section 3 MCU Operating Modes 3.3.6 Pin Functions Table 3.3 lists the pin functions in each operating mode. Table 3.3 Pin Functions in Each Operating Mode (Advanced Mode) MCU Operating Mode PA7 2 Boot mode P*/C 4 ROM disabled C ...
Page 123
Address Map 3.4.1 Address Map Figures 3.1 and 3.2 are the address maps of the H8SX/1544. Mode 2 Boot mode (Advanced mode) H'000000 On-chip ROM (FLASH) 512 kbytes H'080000 External address space/ reserved area* H'FD9000 Reserved area H'FDC000 External ...
Page 124
Section 3 MCU Operating Modes Mode On-chip ROM disabled extended mode (Advanced mode) H'000000 External address space H'FD9000 Reserved area 3 * H'FDC000 External address space H'FF6000 On-chip RAM 24 kbytes/ external address space* H'FFC000 External address ...
Page 125
Figures 3.3 and 3.4 are the address maps of the H8SX/1543. Mode 2 Boot mode (Advanced mode) H'000000 On-chip ROM (FLASH) 384 kbytes H'060000 External address space/ reserved area* H'FD9000 Reserved area* H'FDC000 External address space/ reserved area* H'FF8000 On-chip ...
Page 126
Section 3 MCU Operating Modes Mode On-chip ROM disabled extended mode (Advanced mode) H'000000 External address space H'FD9000 3 Reserved area * H'FDC000 External address space H'FF8000 On-chip RAM 16 kbytes/ external address space* H'FFC000 External address ...
Page 127
Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, and an illegal instruction (general illegal instruction or slot ...
Page 128
Section 4 Exception Handling 4.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector ...
Page 129
Exception Source External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 4 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI DMA ...
Page 130
Section 4 Exception Handling 4.3 Reset A reset has priority over any other exception. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES ...
Page 131
Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, ...
Page 132
Section 4 Exception Handling Bφ RES Address bus RD LHWR, LLWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start ...
Page 133
Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared. For ...
Page 134
Section 4 Exception Handling 4.5 Address Error 4.5.1 Address Error Source Instruction fetch, stack operation, or data read/write shown in table 4.5 may cause an address error. Table 4.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Description ...
Page 135
Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents ...
Page 136
Section 4 Exception Handling 4.6 Interrupts 4.6.1 Interrupt Sources Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 4.7. Table 4.7 Interrupt Sources Type Source NMI NMI pin (external input) Pins IRQ0 to IRQ15 ...
Page 137
The interrupt exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared exception handling vector ...
Page 138
Section 4 Exception Handling 4.7.2 Exception Handling by Illegal Instruction The illegal instructions are general illegal instructions and slot illegal instructions. The exception handling by the general illegal instruction starts when an undefined code is executed. The exception handling by ...
Page 139
Stack Status after Exception Handling Figure 4.3 shows the stack after completion of exception handling. Advanced mode SP Interrupt control mode 0 Note: * Ignored on return. Figure 4.3 Stack Status after Exception Handling 4.9 Usage Note When performing ...
Page 140
Section 4 Exception Handling SP TRAPA instruction executed SP set to H'FFFEFF Legend: CCR : Condition code register PC : Program counter R1L : General register R1L SP : Stack pointer Note: This diagram illustrates an example in which the ...
Page 141
Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). • Priority can be assigned by the ...
Page 142
Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISCR IER Internal interrupt sources Source selector WOVI to WCMI Legend: Interrupt ...
Page 143
Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ15 to IRQ0 Input 5.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) ...
Page 144
Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit 7 6 ⎯ ⎯ Bit Name Initial Value Initial Bit Bit Name Value ...
Page 145
CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DMAC. The interrupt exception handling by the CPU can be given priority over that of the DMAC transfer. The priority level of the ...
Page 146
Section 5 Interrupt Controller Initial Bit Bit Name Value 2 CPUP2 0 1 CPUP1 0 0 CPUP0 0 Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. ...
Page 147
Initial Bit Bit Name Value ⎯ IPR14 1 13 IPR13 1 12 IPR12 1 ⎯ IPR10 1 9 IPR9 1 8 IPR8 1 ⎯ R/W Description R Reserved This is a read-only ...
Page 148
Section 5 Interrupt Controller Initial Bit Bit Name Value 6 IPR6 1 5 IPR5 1 4 IPR4 1 ⎯ IPR2 1 1 IPR1 1 0 IPR0 1 Rev. 3.00 Sep. 24, 2009 Page 100 of 916 REJ09B0381-0300 ...
Page 149
IRQ Enable Register (IER) IER enables or disables interrupt requests IRQ15 to IRQ0. Bit 15 14 Bit Name IRQ15E IRQ14E Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit Name IRQ7E IRQ6E Initial Value 0 0 R/W ...
Page 150
Section 5 Interrupt Controller Initial Bit Bit Name Value 8 IRQ8E 0 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 IRQ0E 0 Rev. 3.00 Sep. 24, ...
Page 151
IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH and ISCRL select the source that generates an interrupt request on pins IRQ15 to IRQ0. Upon changing the setting of ISCR, IRQnF ( 15) in ISR ...
Page 152
Section 5 Interrupt Controller • ISCRH Initial Bit Bit Name Value 15 IRQ15SR 0 14 IRQ15SF 0 13 IRQ14SR 0 12 IRQ14SF 0 11 IRQ13SR 0 10 IRQ13SF 0 9 IRQ12SR 0 8 IRQ12SF 0 Rev. 3.00 Sep. 24, 2009 ...
Page 153
Initial Bit Bit Name Value 7 IRQ11SR 0 6 IRQ11SF 0 5 IRQ10SR 0 4 IRQ10SF 0 3 IRQ9SR 0 2 IRQ9SF 0 1 IRQ8SR 0 0 IRQ8SF 0 R/W Description R/W IRQ11 Sense Control Rise IRQ11 Sense Control Fall ...
Page 154
Section 5 Interrupt Controller • ISCRL Initial Bit Bit Name Value 15 IRQ7SR 0 14 IRQ7SF 0 13 IRQ6SR 0 12 IRQ6SF 0 11 IRQ5SR 0 10 IRQ5SF 0 9 IRQ4SR 0 8 IRQ4SF 0 Rev. 3.00 Sep. 24, 2009 ...
Page 155
Initial Bit Bit Name Value 7 IRQ3SR 0 6 IRQ3SF 0 5 IRQ2SR 0 4 IRQ2SF 0 3 IRQ1SR 0 2 IRQ1SF 0 1 IRQ0SR 0 0 IRQ0SF 0 R/W Description R/W IRQ3 Sense Control Rise IRQ3 Sense Control Fall ...
Page 156
Section 5 Interrupt Controller 5.3.6 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request register. Bit 15 14 Bit Name IRQ15F IRQ14F Initial Value 0 0 R/W R/(W)* R/(W)* Bit 7 6 Bit Name IRQ7F IRQ6F Initial ...
Page 157
Software Standby Release IRQ Enable Register (SSIER) SSIER selects pins used to leave software standby mode from pins IRQ15 to IRQ0. Bit 15 14 Bit Name SSI15 SSI14 Initial Value 0 0 R/W R/W R/W Bit 7 6 Bit ...
Page 158
Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to leave software standby mode. NMI Interrupts (1) Nonmaskable interrupt request (NMI) is the highest-priority ...
Page 159
A block diagram of interrupts IRQn is shown in figure 5.2. Corresponding bit in ICR Input buffer IRQn input Note Figure 5.2 Block Diagram of Interrupts IRQn When ISCR is set so that an IRQn ...
Page 160
Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Table Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control ...
Page 161
Interrupt Source Interrupt Name Reserved Reserved for system use A/D_0 ADI0 A/D_1 ADI1 TPU_0 TGI0A TGI0B TGI0C TGI0D TCI0V TPU_1 TGI1A TGI1B TCI1V TCI1U TPU_2 TGI2A TGI2B TCI2V TCI2U TPU_3 TGI3A TGI3B TGI3C TGI3D TCI3V TPU_4 TGI4A TGI4B TCI4V TCI4U ...
Page 162
Section 5 Interrupt Controller Interrupt Source Interrupt Name TPU_5 TGI5A TGI5B TCI5V TCI5U Reserved Reserved for system use DMAC DMTEND0 DMTEND1 DMTEND2 DMTEND3 Reserved Reserved for system use DMAC DMEEND0 DMEEND1 DMEEND2 DMEEND3 Reserved Reserved for system use SCI_0 ERI_0 ...
Page 163
Interrupt Source Interrupt Name Reserved Reserved for system use SCI_2 ERI_2 RXI_2 TXI_2 TEI_2 Reserved Reserved for system use SCI_4 ERI_4 RXI_4 TXI_4 TEI_4 Reserved Reserved for system use SCI_5 ERI_5 RXI_5 TXI_5 TEI_5 Reserved Reserved for system use IIC2 ...
Page 164
Section 5 Interrupt Controller Interrupt Source Interrupt Name RCAN-ET_0 RM0_0 RCAN-ET_1 RM0_1 RCAN-ET_0 ERS0_0/OVR0_0/RM1_0/ SLE0_0 RCAN-ET_1 ERS0_1/OVR0_1/RM1_1/ SLE0_1 Motor control CMI0_0 PWM_0 Motor control CMI1_0 PWM_1 Watch timer (WAT) WCMI Reserved Reserved for system use 16-bit PWM_0 CMI0_1 16-bit PWM_1 ...
Page 165
Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by ...
Page 166
Section 5 Interrupt Controller IRQ0 Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance Rev. 3.00 Sep. 24, 2009 Page 118 of 916 REJ09B0381-0300 Program execution state Interrupt generated? Yes Yes NMI Yes No Yes IRQ1 ...
Page 167
Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level ( bits) in EXR of the CPU and the IPR setting. There are eight levels ...
Page 168
Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance Rev. 3.00 Sep. 24, 2009 Page 120 of 916 REJ09B0381-0300 Program execution state No Interrupt generated? Yes ...
Page 169
Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on- chip ...
Page 170
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times⎯the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table ...
Page 171
Table 5.5 Number of Execution States in Interrupt Handling Routine On-Chip Symbol Memory Vector fetch Instruction fetch Stack manipulation Legend: m: Number of wait cycles in an external device access. Object ...
Page 172
Section 5 Interrupt Controller 5.6.5 DMAC Activation by Interrupt The DMAC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to the CPU • Activation request to the DMAC • Combination of ...
Page 173
Selection of Interrupt Sources (1) A DMAC activation request source for each channel is specified by DMRSR. The request is passed to the DMAC via a selector. When the DTA bit in DMDR is set to 1, the specified request ...
Page 174
Section 5 Interrupt Controller 5.7 CPU Priority Control Function over DMAC The interrupt controller has a function to control the priority among the DMAC and the CPU by assigning priority levels to the DMAC and CPU. Since the priority level ...
Page 175
Table 5.7 shows the CPU priority control. Table 5.7 CPU Priority Control Interrupt Control Interrupt Interrupt Mode Priority Mask Bit 0 Default I = any IPR setting Table 5.8 shows ...
Page 176
Section 5 Interrupt Controller 5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable ...
Page 177
Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the ...
Page 178
Section 5 Interrupt Controller 5.8.6 Interrupt Flags of Peripheral Modules To clear an interrupt request flag of a peripheral module by the CPU, the flag must be read from after being cleared in the interrupt service routine if a peripheral ...
Page 179
Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus ...
Page 180
Section 6 Bus Controller (BSC) • Multi-clock function The on-chip peripheral functions can be operated in synchronization with the peripheral module clock (Pφ). Accesses to the external address space can be operated in synchronization with the external bus clock (Bφ). ...
Page 181
Register Descriptions The bus controller has the following registers. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register A (WTCRA) • Wait control register B (WTCRB) • Read strobe timing control register ...
Page 182
Section 6 Bus Controller (BSC) 6.2.1 Bus Width Control Register (ABWCR) ABWCR specifies the data bus width for each area in the external address space. Bit 15 14 Bit Name ABWH7 ABWH6 Initial Value 1 1 R/W R/W R/W Bit ...
Page 183
Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space and enables/disables wait cycle insertion. Bit 15 14 Bit Name AST7 AST6 Initial Value 1 1 ...
Page 184
Section 6 Bus Controller (BSC) 6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) WTCRA and WTCRB select the number of program wait cycles for each area in the external address space. • WTCRA Bit 15 14 ⎯ Bit Name ...
Page 185
WTCRA Initial Bit Bit Name Value ⎯ W72 1 13 W71 1 12 W70 1 ⎯ W62 1 9 W61 1 8 W60 1 ⎯ R/W Description R Reserved This is ...
Page 186
Section 6 Bus Controller (BSC) Initial Bit Bit Name Value 6 W52 1 5 W51 1 4 W50 1 ⎯ W42 1 1 W41 1 0 W40 1 Rev. 3.00 Sep. 24, 2009 Page 138 of 916 ...
Page 187
WTCRB Initial Bit Bit Name Value ⎯ W32 1 13 W31 1 12 W30 1 ⎯ W22 1 9 W21 1 8 W20 1 ⎯ R/W Description R Reserved This is ...
Page 188
Section 6 Bus Controller (BSC) Initial Bit Bit Name Value 6 W12 1 5 W11 1 4 W10 1 ⎯ W02 1 1 W01 1 0 W00 1 Rev. 3.00 Sep. 24, 2009 Page 140 of 916 ...
Page 189
Read Strobe Timing Control Register (RDNCR) RDNCR selects the negation timing of the read strobe signal (RD) when reading the external address spaces specified as a basic bus interface or the address/data multiplexed I/O interface. Bit 15 14 Bit ...
Page 190
Section 6 Bus Controller (BSC) Bφ RD RDNn = 0 Data RD RDNn = 1 Data Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) 6.2.5 Idle Control Register (IDLCR) IDLCR specifies the idle cycle insertion conditions and ...
Page 191
Initial Bit Bit Name Value 15 IDLS3 1 14 IDLS2 1 13 IDLS1 1 12 IDLS0 1 11 IDLCB1 1 10 IDLCB0 1 R/W Description R/W Idle Cycle Insertion 3 Inserts an idle cycle between the bus cycles when the ...
Page 192
Section 6 Bus Controller (BSC) Initial Bit Bit Name Value 9 IDLCA1 1 8 IDLCA0 1 7 IDLSEL7 0 6 IDLSEL6 0 5 IDLSEL5 0 4 IDLSEL4 0 3 IDLSEL3 0 2 IDLSEL2 0 1 IDLSEL1 0 0 IDLSEL0 0 ...
Page 193
Initial Bit Bit Name Value ⎯ 15, 14 All 0 ⎯ 13, 12 All 0 ⎯ 11, 10 All 0 9 WDBE 0 ⎯ DKC 0 ⎯ ⎯ All 0 R/W Description ...
Page 194
Section 6 Bus Controller (BSC) 6.2.7 Bus Control Register 2 (BCR2) BCR2 is used for bus arbitration control of the CPU and DMAC, and enabling/disabling of the write data buffer function to the peripheral modules. Bit 7 6 ⎯ ⎯ ...
Page 195
Endian Control Register (ENDIANCR) ENDIANCR selects the endian format for each area of the external address space. Though the data format of this LSI is big endian, data can be transferred in the little endian format during external address ...
Page 196
Section 6 Bus Controller (BSC) 6.3 Bus Configuration Figure 6.3 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following three types. • Internal system bus A bus that connects the CPU, ...
Page 197
Multi-Clock Function and Number of Access Cycles The internal functions of this LSI operate synchronously with the system clock (Iφ), the peripheral module clock (Pφ), or the external bus clock (Bφ). Table 6.1 shows the synchronization clock and their ...
Page 198
Section 6 Bus Controller (BSC) For example external address space access where the frequency rate of Iφ and Bφ the operation is performed in synchronization with Bφ. In this case, external 2-state access space ...
Page 199
Divided clock synchronization cycle T sy Iφ Bφ Address AS RD Read D15 LHWR LLWR Write D15 Figure 6.5 System Clock: External Bus Clock = 2:1, External 3-State Access T ...
Page 200
Section 6 Bus Controller (BSC) 6.5 External Bus 6.5.1 Input/Output Pins Table 6.2 shows the pin configuration of the bus controller and table 6.3 shows the pin functions on each interface. Table 6.2 Pin Configuration Name Address strobe Read strobe ...