MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 47

• Manufacturer Part Number: MC68LK332ACAG16
• Description: IC MCU 32BIT LV AMASK 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68LK332ACAG16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16.78MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Interface Type: QSPI, SCI, UART
• Minimum Operating Temperature: - 40 C
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6 Instruction Set Summary
MC68332
MC68332TS/D
ANDI to SR1
ANDI to CCR
Instruction
CMPM
ABCD
ADDQ
BCHG
BGND
CMPA
ADDA
ADDX
BCLR
CHK2
CMP2
BKPT
BSET
BTST
ADDI
ANDI
CMPI
ADD
AND
CHK
CMP
ASR
BRA
BSR
CLR
ASL
Bcc
1
# <data>, <ea>
# <data>, <ea>
# <data>, <ea>
# <data>, <ea>
# <data>, <ea>
# <data>, <ea>
# <data>, <ea>
# <data>, CCR
#<data>, <ea>
(An) , (An)
# <data>, SR
# <data>, Dn
# <data>, Dn
(An),
(An),
Dn, <ea>
<ea>, Dn
<ea>, An
<ea>, Dn
Dn, <ea>
Dn, <ea>
Dn, <ea>
Dn, <ea>
Dn, <ea>
<ea>, Dn
<ea>, Rn
<ea>, Dn
<ea>, An
<ea>, Rn
# <data>
Syntax
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Í
Í
none
Í
label
label
label
Freescale Semiconductor, Inc.
For More Information On This Product,
(An)
(An)
Table 20 Instruction Set Summary
8, 16, 32
Go to: www.freescale.com
Operand Size
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16, 32
16, 32
16, 32
8, 32
8, 32
8, 32
8, 32
none
none
8, 32
8, 32
8, 32
8, 32
16
16
16
8
8
8
Source
Source
Source
Immediate data
Immediate data
Source
Source Destination
Data Destination
Source CCR
Source SR
If condition true, then PC
bit number of destination
0
If background mode enabled, then enter background
mode, else format/vector
PC
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal instruction
PC
1
SP
If Dn < 0 or Dn > (ea), then CHK exception
If Rn < lower bound or Rn > upper bound, then
CHK exception
0
(Destination
(Destination
(Destination
(Destination
Lower bound
bit number of destination
bit number of destination
bit number of destination
Z
bit of destination
bit of destination
Destination
d
4
10
X/C
(SSP); SR
Destination
Destination
Destination
SP; PC
PC
Destination
Source), CCR shows results
Source), CCR shows results
Data), CCR shows results
Source), CCR shows results
Rn
SR
CCR
Destination
Destination
Upper bound, CCR shows result
(SP); PC
Operation
Destination
10
X
Destination
(SSP); (vector)
Destination
Destination
d
X
Destination
(SSP);
PC
Destination
d
Z
Destination
Destination
Z;
Z
PC
bit of destinatio
MOTOROLA
X/C
PC
0
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