DF61663W50FPV Renesas Electronics America, DF61663W50FPV Datasheet - Page 32

• Manufacturer Part Number: DF61663W50FPV
• Description: IC H8SX/1663 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61663W50FPV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2... 119
Figure 5.5 Interrupt Exception Handling .................................................................................... 120
Figure 5.6 Block Diagram of DTC, DMAC, and Interrupt Controller ....................................... 123
Figure 5.7 Conflict between Interrupt Generation and Disabling............................................... 128
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller.............................................................................. 133
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) .......................... 143
Figure 6.3 CS and Address Assertion Period Extension
Figure 6.4 RAS Assertion Timing
Figure 6.5 Internal Bus Configuration ........................................................................................ 168
Figure 6.6 System Clock: External Bus Clock = 4:1, External 2-State Access .......................... 171
Figure 6.7 System Clock: External Bus Clock = 2:1, External 3-State Access .......................... 172
Figure 6.8 Address Space Area Division.................................................................................... 177
Figure 6.9 CSn Signal Output Timing (n = 0 to 7) ..................................................................... 178
Figure 6.10 Timing When CS Signal is Output to the Same Pin................................................ 179
Figure 6.11 Access Sizes and Data Alignment Control for 8-Bit Access Space
Figure 6.12 Access Sizes and Data Alignment Control for 8-Bit Access Space
Figure 6.13 Access Sizes and Data Alignment Control for 16-Bit Access Space
Figure 6.14 Access Sizes and Data Alignment Control for 16-Bit Access Space
Figure 6.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address)........... 193
Figure 6.16 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address) ............ 194
Figure 6.17 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address) ......... 195
Figure 6.18 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address)........... 196
Figure 6.19 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address) .......... 197
Figure 6.20 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address) ......... 198
Figure 6.21 Example of Wait Cycle Insertion Timing................................................................ 200
Figure 6.22 Example of Read Strobe Timing ............................................................................. 201
Figure 6.23 Example of Timing when Chip Select Assertion Period is Extended ..................... 203
Figure 6.24 DACK Signal Output Timing.................................................................................. 204
Figure 6.25 16-Bit 2-State Access Space Bus Timing................................................................ 207
Figure 6.26 16-Bit 3-State Access Space Bus Timing................................................................ 208
Figure 6.27 Example of Wait Cycle Insertion Timing................................................................ 210
Figure 6.28 DACK Signal Output Timing.................................................................................. 212
Figure 6.29 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)................ 215
Rev.1.00 Jun. 07, 2006 Page xxx of lii
(Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0)................. 145
(Column Address Output for 2 cycles in Full Access Mode) ................................... 160
(Big Endian) ........................................................................................................... 189
(Little Endian)......................................................................................................... 190
(Big Endian) ........................................................................................................... 191
(Little Endian)......................................................................................................... 191