DF61663W50FPV Renesas Electronics America, DF61663W50FPV Datasheet - Page 297

• Manufacturer Part Number: DF61663W50FPV
• Description: IC H8SX/1663 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61663W50FPV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other
spaces may be accessed. The RAS signal can be held low during other space accesses. The fast-
page mode access can be resumed (burst access) when the same row address in the DRAM space
is accessed.
(a)
Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode.
The RCDM bit is enabled only when the BE bit is set to 1.
The fast-page mode access (burst access) is resumed when the row addresses of the current cycle
and previous cycle are the same. While other spaces are accessed when the DRAM space access is
halted, the RAS signal must be low. Figure 6.50 shows a timing example of RAS down mode.
The RAS signal goes high under the following conditions.
• When a refresh cycle is performed during RAS down mode
• When a self-refresh is performed
• When a transition to software standby mode is made
• When the external bus requested by the BREQ signal is released
• When either the RCDM or BE bit is cleared to 0
If a transition to the all-module clock-stop mode is made during RAS down mode, clocks are
stopped with the RAS signal driven low. To make a transition with the RAS signal driven high,
clear the RCDM bit to 0 before execution of the SLEEP instruction.
Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see
section 22, Clock Pulse Generator.
RAS Down Mode and RAS Up Mode
RAS Down Mode
Rev.1.00 Jun. 07, 2006 Page 243 of 1102
Section 6 Bus Controller (BSC)
REJ09B0294-0100