DF61663W50FPV Renesas Electronics America, DF61663W50FPV Datasheet - Page 15

• Manufacturer Part Number: DF61663W50FPV
• Description: IC H8SX/1663 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61663W50FPV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7
6.8
6.9
6.10 DRAM Interface ................................................................................................................ 228
6.6.6
6.6.7
Byte Control SRAM Interface ........................................................................................... 205
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.7.8
Burst ROM Interface.......................................................................................................... 213
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.8.7
Address/Data Multiplexed I/O Interface............................................................................ 218
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
6.9.6
6.9.7
6.9.8
6.9.9
6.9.10 DACK Signal Output Timing ............................................................................... 227
6.10.1 Setting DRAM Space............................................................................................ 228
6.10.2 Address Multiplexing............................................................................................ 228
6.10.3 Data Bus................................................................................................................ 229
6.10.4 I/O Pins Used for DRAM Interface ...................................................................... 229
6.10.5 Basic Timing......................................................................................................... 230
6.10.6 Controlling Column Address Output Cycle.......................................................... 231
6.10.7 Controlling Row Address Output Cycle ............................................................... 232
6.10.8 Controlling Precharge Cycle................................................................................. 234
6.10.9 Wait Control ......................................................................................................... 235
Extension of Chip Select (CS) Assertion Period................................................... 202
DACK Signal Output Timing ............................................................................... 204
Byte Control SRAM Space Setting....................................................................... 205
Data Bus................................................................................................................ 205
I/O Pins Used for Byte Control SRAM Interface ................................................. 206
Basic Timing......................................................................................................... 207
Wait Control ......................................................................................................... 209
Read Strobe (RD).................................................................................................. 211
Extension of Chip Select (CS) Assertion Period................................................... 211
DACK Signal Output Timing ............................................................................... 211
Burst ROM Space Setting ..................................................................................... 213
Data Bus................................................................................................................ 213
I/O Pins Used for Burst ROM Interface................................................................ 214
Basic Timing......................................................................................................... 215
Wait Control ......................................................................................................... 217
Read Strobe (RD) Timing..................................................................................... 217
Extension of Chip Select (CS) Assertion Period................................................... 217
Address/Data Multiplexed I/O Space Setting ....................................................... 218
Address/Data Multiplex ........................................................................................ 218
Data Bus................................................................................................................ 218
I/O Pins Used for Address/Data Multiplexed I/O Interface .................................. 219
Basic Timing......................................................................................................... 220
Address Cycle Control.......................................................................................... 222
Wait Control ......................................................................................................... 223
Read Strobe (RD) Timing.................................................................................... 223
Extension of Chip Select (CS) Assertion Period................................................... 225
Rev.1.00 Jun. 07, 2006 Page xiii of lii