DF61663W50FPV Renesas Electronics America, DF61663W50FPV Datasheet - Page 13

• Manufacturer Part Number: DF61663W50FPV
• Description: IC H8SX/1663 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61663W50FPV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.5
4.6
4.7
4.8
4.9
Section 5 Interrupt Controller ..............................................................................93
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Address Error ....................................................................................................................... 84
4.5.1
4.5.2
Interrupts.............................................................................................................................. 86
4.6.1
4.6.2
Instruction Exception Handling ........................................................................................... 87
4.7.1
4.7.2
4.7.3
Stack Status after Exception Handling................................................................................. 90
Usage Note........................................................................................................................... 91
Features................................................................................................................................ 93
Input/Output Pins ................................................................................................................. 95
Register Descriptions ........................................................................................................... 95
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
Interrupt Sources................................................................................................................ 109
5.4.1
5.4.2
Interrupt Exception Handling Vector Table....................................................................... 111
Interrupt Control Modes and Interrupt Operation .............................................................. 116
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
CPU Priority Control Function Over DTC and DMAC..................................................... 125
Usage Notes ....................................................................................................................... 128
5.8.1
5.8.2
5.8.3
Address Error Source.............................................................................................. 84
Address Error Exception Handling ......................................................................... 85
Interrupt Sources..................................................................................................... 86
Interrupt Exception Handling.................................................................................. 87
Trap Instruction....................................................................................................... 87
Sleep Instruction Exception Handling .................................................................... 88
Exception Handling by Illegal Instruction .............................................................. 89
Interrupt Control Register (INTCR) ....................................................................... 96
CPU Priority Control Register (CPUPCR) ............................................................. 97
Interrupt Priority Registers A to I, K, L, Q, and R
(IPRA to IPRI, IPRK, IPRL, IPRQ, and IPRR)...................................................... 98
IRQ Enable Register (IER) ................................................................................... 100
IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 102
IRQ Status Register (ISR)..................................................................................... 106
Software Standby Release IRQ Enable Register (SSIER) .................................... 107
External Interrupts ................................................................................................ 109
Internal Interrupts ................................................................................................. 110
Interrupt Control Mode 0 ...................................................................................... 116
Interrupt Control Mode 2 ...................................................................................... 118
Interrupt Exception Handling Sequence ............................................................... 120
Interrupt Response Times ..................................................................................... 121
DTC and DMAC Activation by Interrupt ............................................................. 122
Conflict between Interrupt Generation and Disabling .......................................... 128
Instructions that Disable Interrupts ....................................................................... 129
Times when Interrupts are Disabled ..................................................................... 129
Rev.1.00 Jun. 07, 2006 Page xi of lii