DF61663W50FPV Renesas Electronics America, DF61663W50FPV Datasheet
DF61663W50FPV
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DF61663W50FPV Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8SX/1663Group 32 Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series H8SX/1663 R5F61663 H8SX/1664 R5F61664 Rev.1.00 2006.06 ...
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Rev.1.00 Jun. 07, 2006 Page ii of lii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8SX/1663 Group is a single-chip microcomputer made up of the high-speed internal 32-bit H8SX CPU as its core, and the peripheral functions required to configure a system. The H8SX CPU is upward compatible with the H8/300, H8/300H, and H8S ...
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H8SX/1663 Group manuals: Document Title H8SX/1663 Group Hardware Manual H8SX Family Software Manual Document No. This manual REJ09B0102 Rev.1.00 Jun. 07, 2006 Page vii of lii ...
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Rev.1.00 Jun. 07, 2006 Page viii of lii ...
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Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.2 Block Diagram ....................................................................................................................... 2 1.3 Pin Assignments..................................................................................................................... 3 1.3.1 Pin Assignments ....................................................................................................... 3 1.3.2 Pin Configuration in Each Operating Mode.............................................................. 4 1.3.3 Pin Functions ............................................................................................................ 9 Section 2 CPU......................................................................................................21 2.1 Features................................................................................................................................ 21 2.2 ...
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Register Indirect with Displacement —@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn) .................................................................................................... 56 2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 56 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− ...
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Address Error ....................................................................................................................... 84 4.5.1 Address Error Source.............................................................................................. 84 4.5.2 Address Error Exception Handling ......................................................................... 85 4.6 Interrupts.............................................................................................................................. 86 4.6.1 Interrupt Sources..................................................................................................... 86 4.6.2 Interrupt Exception Handling.................................................................................. 87 4.7 Instruction Exception Handling ........................................................................................... 87 4.7.1 Trap Instruction....................................................................................................... 87 4.7.2 ...
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Interrupts during Execution of EEPMOV Instruction........................................... 129 5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions.................... 129 5.8.6 Interrupts of Peripheral Modules .......................................................................... 130 Section 6 Bus Controller (BSC) ........................................................................ 131 6.1 Features.............................................................................................................................. 131 6.2 Register Descriptions ......................................................................................................... 134 ...
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Extension of Chip Select (CS) Assertion Period................................................... 202 DACK Signal Output Timing ............................................................................... 204 6.6.7 6.7 Byte Control SRAM Interface ........................................................................................... 205 6.7.1 Byte Control SRAM Space Setting....................................................................... 205 6.7.2 Data Bus................................................................................................................ 205 6.7.3 I/O Pins Used for Byte ...
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Controlling Byte and Word Accesses ................................................................... 238 6.10.11 Burst Access Operation ........................................................................................ 240 6.10.12 Refresh Control..................................................................................................... 246 6.10.13 DRAM Interface and Single Address Transfer by DMAC ................................... 251 6.11 Synchronous DRAM Interface........................................................................................... 254 6.11.1 Setting SDRAM space .......................................................................................... 254 ...
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Input/Output Pins ............................................................................................................... 320 7.3 Register Descriptions ......................................................................................................... 321 7.3.1 DMA Source Address Register (DSAR)............................................................... 322 7.3.2 DMA Destination Address Register (DDAR)....................................................... 323 7.3.3 DMA Offset Register (DOFR).............................................................................. 324 7.3.4 DMA Transfer Count Register (DTCR) ............................................................... 325 7.3.5 DMA ...
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DTC enable registers and H (DTCERA to DTCERE, DTCERG, and DTCERH) ...................................................................................................... 402 8.2.8 DTC Control Register (DTCCR) .......................................................................... 403 8.2.9 DTC Vector Base Register (DTCVBR)................................................................ 405 8.3 Activation Sources............................................................................................................. 405 8.4 Location of Transfer ...
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Input Buffer Control Register (PnICR and M)..... 439 9.1.5 Pull-Up MOS Control Register (PnPCR and I)........................... 440 9.1.6 Open-Drain Control Register ...
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Timer Status Register (TSR)................................................................................. 530 10.3.6 Timer Counter (TCNT)......................................................................................... 534 10.3.7 Timer General Register (TGR) ............................................................................. 534 10.3.8 Timer Start Register (TSTR) ................................................................................ 535 10.3.9 Timer Synchronous Register (TSYR)................................................................... 536 10.4 Operation ........................................................................................................................... 537 10.4.1 Basic Functions..................................................................................................... 537 10.4.2 ...
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Output Data Registers H, L (PODRH, PODRL)................................................... 587 11.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 588 11.3.4 PPG Output Control Register (PCR) .................................................................... 591 11.3.5 PPG Output Mode Register (PMR) ...................................................................... 592 11.4 Operation ........................................................................................................................... 594 11.4.1 ...
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Compare Match Count Mode................................................................................ 629 12.7 Interrupt Sources................................................................................................................ 629 12.7.1 Interrupt Sources and DTC Activation ................................................................. 629 12.7.2 A/D Converter Activation..................................................................................... 630 12.8 Usage Notes ....................................................................................................................... 631 12.8.1 Notes on Setting Cycle ......................................................................................... 631 12.8.2 Conflict between TCNT Write ...
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Notes on Register Access...................................................................................... 649 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 650 14.6.3 Changing Values of Bits CKS2 to CKS0.............................................................. 650 14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 650 14.6.5 Internal Reset in ...
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Serial Data Reception (Clocked Synchronous Mode) (SCI_0 and 4 only)....................................................................................... 719 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) (SCI_0 and 4 only)...................................... 720 15.7 Operation in Smart Card Interface Mode........................................................................... 722 15.7.1 ...
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Interrupt Select Register 1 (ISR1)......................................................................... 760 16.3.6 Interrupt Select Register 2 (ISR2)......................................................................... 761 16.3.7 Interrupt Enable Register 0 (IER0) ....................................................................... 762 16.3.8 Interrupt Enable Register 1 (IER1) ....................................................................... 763 16.3.9 Interrupt Enable Register 2 (IER2) ....................................................................... 763 16.3.10 EP0i ...
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DMA Transfer for Endpoint 1 .............................................................................. 809 16.8.3 DMA Transfer for Endpoint 2 .............................................................................. 810 16.9 Example of USB External Circuitry .................................................................................. 811 16.10 Usage Notes ....................................................................................................................... 813 16.10.1 Receiving Setup Data............................................................................................ 813 16.10.2 Clearing the FIFO ................................................................................................. 813 ...
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Register Descriptions ......................................................................................................... 851 18.3.1 A/D Data Registers (ADDRA to ADDRH) .............................................. 852 18.3.2 A/D Control/Status Register (ADCSR) ................................................................ 853 18.3.3 A/D Control Register (ADCR) ............................................................................. 855 18.4 Operation ........................................................................................................................... 856 18.4.1 Single Mode.......................................................................................................... 856 18.4.2 ...
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Input/Output Pins............................................................................................................... 883 21.6 Register Descriptions ......................................................................................................... 884 21.6.1 Programming/Erasing Interface Registers ............................................................ 885 21.6.2 Programming/Erasing Interface Parameters ......................................................... 891 21.6.3 RAM Emulation Register (RAMER).................................................................... 902 21.7 On-Board Programming Mode .......................................................................................... 903 21.7.1 SCI Boot Mode ..................................................................................................... 903 21.7.2 ...
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Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) .............. 976 23.2.3 Module Stop Control Register C (MSTPCRC)..................................................... 979 23.3 Multi-Clock Function......................................................................................................... 980 23.3.1 Switching of Main Clock ...................................................................................... 980 23.3.2 Switching to Subclock .......................................................................................... 980 23.4 Module ...
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Bus Timing ......................................................................................................... 1047 25.3.4 DMAC Timing.................................................................................................... 1074 25.3.5 Timing of On-Chip Peripheral Modules ............................................................. 1077 25.4 USB Characteristics ......................................................................................................... 1082 25.5 A/D Conversion Characteristics....................................................................................... 1084 25.6 D/A Conversion Characteristics....................................................................................... 1084 25.7 Flash Memory Characteristics ......................................................................................... 1085 25.7.1 H8SX/1663 ...
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Section 1 Overview Figure 1.1 Block Diagram .............................................................................................................. 2 Figure 1.2 Pin Assignments ............................................................................................................ 3 Section 2 CPU Figure 2.1 CPU Operating Modes ................................................................................................ 23 Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 24 Figure 2.3 Stack Structure (Normal Mode) .................................................................................. ...
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Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2... 119 Figure 5.5 Interrupt Exception Handling .................................................................................... 120 Figure 5.6 Block Diagram of DTC, DMAC, and Interrupt Controller ....................................... 123 Figure 5.7 Conflict between Interrupt Generation ...
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Figure 6.30 Example of Burst ROM Access Timing (ASTn = 0, One Burst Cycle) .................. 216 Figure 6.31 8-Bit Access Space Access Timing (ABWHn = 1, ABWLn = 1) ........................... 220 Figure 6.32 16-Bit Access Space Access Timing (ABWHn = ...
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Figure 6.63 Read Timing Example of Row Address Output Retained for 1 Clock Cycle (RCD1 = 0, RCD0 = 1, CAS Latency = 2) ............................................................. 261 Figure 6.64 Write Timing Example of Row Address Output Retained for 1 Clock Cycle ...
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Figure 6.93 Example of Idle Cycle Operation (Write after Single Address Transfer Write)...... 296 Figure 6.94 Idle Cycle Insertion Example .................................................................................. 297 Figure 6.95 Relationship between Chip Select (CS) and Read (RD).......................................... 298 Figure 6.96 Example of DRAM Full Access ...
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Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement)............. 372 Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access ........................... 373 Figure 7.28 Example ...
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Figure 8.12 DTC Operation Timing (Example of Short Address Mode in Block Transfer Mode with Block Size of 2) ........................................................ 419 Figure 8.13 DTC Operation Timing (Example of Short Address Mode in Chain Transfer) .................................................................................................... 420 Figure 8.14 DTC Operation ...
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Figure 10.32 Output Compare Output Timing ........................................................................... 567 Figure 10.33 Input Capture Input Signal Timing........................................................................ 567 Figure 10.34 Counter Clear Timing (Compare Match) .............................................................. 568 Figure 10.35 Counter Clear Timing (Input Capture) .................................................................. 568 Figure 10.36 Buffer Operation Timing (Compare ...
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Figure 12.4 Block Diagram of 8-Bit Timer Module (Unit 3) ..................................................... 609 Figure 12.5 Example of Pulse Output......................................................................................... 624 Figure 12.6 Example of Reset Input ........................................................................................... 624 Figure 12.7 Count Timing for Internal Clock Input.................................................................... 625 Figure 12.8 Count Timing ...
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Figure 15.10 Example of Serial Transmission Flowchart........................................................... 704 Figure 15.11 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit).................................................. 705 Figure 15.12 Sample Serial Reception Flowchart (1)................................................................. 707 Figure 15.12 Sample Serial Reception Flowchart (2)................................................................. ...
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Figure 15.41 Port Pin States during Software Standby Mode Transition (Internal Clock, Clocked Synchronous Transmission) (Setting is Prohibited in SCI_5 and SCI_6) .......................................................... 743 Figure 15.42 Sample Flowchart for Software Standby Mode Transition during Reception....... 743 Figure 15.43 Block Diagram ...
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Figure 17 Bus Timing........................................................................................................ 833 Figure 17.5 Master Transmit Mode Operation Timing 1............................................................ 835 Figure 17.6 Master Transmit Mode Operation Timing 2............................................................ 835 Figure 17.7 Master Receive Mode Operation Timing 1 ............................................................. 837 Figure 17.8 Master Receive ...
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Figure 21.9 System Configuration in USB Boot Mode .............................................................. 907 Figure 21.10 USB Boot Mode State Transition Diagram ........................................................... 909 Figure 21.11 Programming/Erasing Flow................................................................................... 911 Figure 21.12 RAM Map when Programming/Erasing is Executed ............................................ 912 Figure 21.13 Programming Procedure in ...
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Figure 23.7 When Canceling Factor Interrupt is Generated Immediately before SLEEP Instruction Execution (Sleep Instruction Exception Handling Initiated) ................ 991 Section 25 Electrical Characteristics Figure 25.1 Output Load Circuit .............................................................................................. 1043 Figure 25.2 External Bus Clock Timing ................................................................................... 1044 Figure ...
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Figure 25.35 DMAC (DREQ) Input Timing ............................................................................ 1074 Figure 25.36 DMAC (TEND) Output Timing .......................................................................... 1075 Figure 25.37 DMAC Single-Address Transfer Timing: Two-State Access ............................. 1075 Figure 25.38 DMAC Single-Address Transfer Timing: Three-State Access ........................... 1076 Figure 25.39 I/O Port ...
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Section 1 Overview Table 1.1 Pin Configuration in Each Operating Mode.............................................................. 4 Table 1.2 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 38 Table 2.2 Combinations of Instructions and Addressing Modes (1)....................................... 40 Table 2.2 Combinations ...
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Section 5 Interrupt Controller Table 5.1 Pin Configuration.................................................................................................... 95 Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority........................ 111 Table 5.3 Interrupt Control Modes ....................................................................................... 116 Table 5.4 Interrupt Response Times ..................................................................................... 121 Table 5.5 Number of Execution States ...
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Table 6.31 Pin States in Idle Cycle ......................................................................................... 303 Table 6.32 Pin States in Bus Released State ........................................................................... 305 Table 6.33 Number of Access Cycles for On-Chip Memory Spaces...................................... 308 Table 6.34 Number of Access Cycles for Registers of On-Chip ...
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Table 10.8 TPSC2 to TPSC0 (Channel 2) .............................................................................. 507 Table 10.9 TPSC2 to TPSC0 (Channel 3) .............................................................................. 507 Table 10.10 TPSC2 to TPSC0 (Channel 4) .......................................................................... 508 Table 10.11 TPSC2 to TPSC0 (Channel 5) .......................................................................... 508 Table 10.12 MD3 to ...
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Table 12.7 Switching of Internal Clock and TCNT Operation ............................................... 634 Section 13 32K Timer (TM32K) Table 13.1 TM32K Interrupt Source....................................................................................... 640 Section 14 Watchdog Timer (WDT) Table 14.1 Pin Configuration.................................................................................................. 642 Table 14.2 WDT Interrupt Source .......................................................................................... 648 Section ...
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Table 17.2 Transfer Rate ........................................................................................................ 822 Table 17.3 Interrupt Requests ................................................................................................. 847 Table 17.4 Time for Monitoring SCL..................................................................................... 848 Section 18 A/D Converter Table 18.1 Pin Configuration.................................................................................................. 851 Table 18.2 Analog Input Channels and Corresponding ADDR Registers .............................. 852 Table ...
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Table 23.2 Oscillation Settling Time Settings ........................................................................ 984 φ Pin (PA7) State in Each Processing State .......................................................... 992 Table 23.3 φ Pin (PB7) State in Each Processing State (SDRAM Interface Enabled)............ 992 Table 23.4 Section 25 Electrical Characteristics Table 25.1 ...
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Features • 32-bit high-speed H8SX CPU Upward compatible with the H8/300 CPU, H8/300H CPU, and H8S CPU Object programs for those CPUs are executable Sixteen 16-bit general registers 87 basic instructions • Extensive peripheral functions DMA controller (DMAC) Data ...
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Section 1 Overview Package LQFP-144 Note: * Pb-free version 1.2 Block Diagram RAM ROM H8SX CPU DTC Main clock oscillator Subclock oscillator [Legend] CPU: Central processing unit DTC: Data transfer controller BSC: Bus controller DMAC: DMA controller WDT: Watchdog timer ...
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Pin Assignments 1.3.1 Pin Assignments 108 107 106 105 104 103 102 101 100 P62/TMO2/SCK4/DACK2/IRQ10-B/TRST 109 PLLVCC 110 P63/TMRI3/DREQ3/IRQ11-B/TMS 111 PLLVSS 112 P64/TMCI3/TEND3/TDI 113 P65/TMO3/DACK3/TCK 114 MD0 115 ...
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Section 1 Overview 1.3.2 Pin Configuration in Each Operating Mode Table 1.1 Pin Configuration in Each Operating Mode Pin No. Modes PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B 2 PB2/CS2-A/CS6-A/RAS 3 PB3/CS3-A/CS7-A/CAS 4 VSS 5 PB7/SDRAMφ 6 VCC 7 MD2 8 PM0/TxD6 ...
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Pin No. Modes PD7/A7 31 PD6/A6 32 VSS 33 PD5/A5 34 PD4/A4 35 PD3/A3 36 PD2/A2 37 PD1/A1 38 PD0/A0 39 EMLE 40 PM3 41 PM4 42 DrVCC 43 USD+ 44 USD- 45 DrVSS 46 VBUS ...
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Section 1 Overview Pin No. Modes NMI 62 P33/PO11/TIOCC0/TIOCD0/TCLKB-A/DREQ1-B P33/PO11/TIOCC0/TIOCD0/TCLKB-A/DREQ1-B 63 P34/PO12/TIOCA1/TEND1-B 64 VCC 65 PH0/D0 66 PH1/D1 67 PH2/D2 68 PH3/D3 69 VSS 70 PH4/D4 71 PH5/D5 72 PH6/D6 73 PH7/D7 74 VCC 75 PI0/D8 ...
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Pin No. Modes VCL 93 P14/DREQ1-A/IRQ4-A/TCLKA-B/TxD5/IrTxD/ SDA1 94 P15/TEND1-A/IRQ5-A/TCLKB-B/RxD5/IrRxD/ SCL1 WDTOVF/TDO 95 96 VSS 97 XTAL 98 EXTAL 99 VCC 100 P16/DACK1-A/IRQ6-A/TCLKC-B/SDA0 101 P17/IRQ7-A/TCLKD-B/SCL0 STBY 102 103 VSS 104 P35/PO13/TIOCA1/TIOCB1/TCLKC-A/DACK1-B 105 P36/PO14/TIOCA2 106 P37/PO15/TIOCA2/TIOCB2/TCLKD-A 107 P60/TMRI2/TxD4/DREQ2/IRQ8-B ...
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Section 1 Overview Pin No. Modes 121 AVCC 122 P53/AN3/IRQ3-B 123 AVSS 124 P54/AN4/IRQ4-B 125 Vref 126 P55/AN5/IRQ5-B 127 P56/AN6/DA0/IRQ6-B 128 P57/AN7/DA1/IRQ7-B 129 MD1 130 PB4/CS4-B/WE 131 PB5/OE/CKE 132 PB6/CS6-D/(RD/WR-B) 133 MD3 134 PA0/BREQO/BS-A 135 PA1/BACK/(RD/WR-A) 136 ...
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Pin Functions Table 1.2 Pin Functions Classification Abbreviation Power supply PLLV CC PLLV SS DrVCC DrVSS Clock XTAL EXTAL OSC1 OSC2 Bφ SDRAMφ Operating mode MD3 control MD2 MD1 MD0 MD_CLK Pin No. ...
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Section 1 Overview Classification Abbreviation RES System control STBY EMLE TRST On-chip emulator TMS TDI TCK TDO Address bus A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 ...
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Classification Abbreviation Data bus D15 D14 D13 D12 D11 D10 BREQ Bus control BREQO BACK BS-A/BS RD/WR-A/RD/WR-B LHWR LLWR Pin No. (FP-144LV) I/O Description 83 Input/ Bidirectional ...
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Section 1 Overview Classification Abbreviation LUB Bus control LLB CS0 CS1 CS2-A/CS2-B CS3-A CS4-A/CS4-B CS5-A/CS5-B CS6-A/CS6-B/CS6-D CS7-A/CS7-B WAIT RAS CAS WE OE/CKE Rev.1.00 Jun. 07, 2006 Page 12 of 1102 REJ09B0294-0100 Pin No. (FP-144LV) I/O Description 138 Output Strobe signal ...
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Classification Abbreviation LUCAS/DQMLU Bus control LLCAS/DQMLL Interrupt NMI IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7-A/IRQ7-B IRQ6-A/IRQ6-B IRQ5-A/IRQ5-B IRQ4-A/IRQ4-B IRQ3-A/IRQ3-B IRQ2-A/IRQ2-B IRQ1-A/IRQ1-B IRQ0-A/IRQ0-B DREQ0-A/DREQ0-B DMA controller DREQ1-A/DREQ1-B (DMAC) DREQ2 DREQ3 DACK0-A/DACK0-B DACK1-A/DACK1-B DACK2 DACK3 TEND0-A/TEND0-B TEND1-A/TEND1-B TEND2 TEND3 Pin No. (FP-144LV) I/O Description ...
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Section 1 Overview Classification Abbreviation 16-bit timer TCLKA-A/TCLKA-B pulse unit TCLKB-A/TCLKB-B (TPU) TCLKC-A/TCLKC-B TCLKD-A/TCLKD-B TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Programmable PO15 pulse generator PO14 (PPG) PO13 PO12 PO11 PO10 ...
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Classification Abbreviation 8-bit timer TMO0 (TMR) TMO1 TMO2 TMO3 TMCI0 TMCI1 TMCI2 TMCI3 TMRI0 TMRI1 TMRI2 TMRI3 WDTOVF Watchdog timer (WDT) Serial TxD0 communication TxD1 interface (SCI) TxD2 TxD4 TxD5 TxD6 RxD0 RxD1 RxD2 RxD4 RxD5 RxD6 SCK0 SCK1 SCK2 ...
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Section 1 Overview Classification Abbreviation bus interface SCL0, SCL1 2 (IIC2) SDA0, SDA1 Universal Serial USD+ Bus Interface USD− (USB) VBUS A/D converter AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 ADTRG0 D/A converter DA1 DA0 A/D ...
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Classification Abbreviation I/O port P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 P37 P36 P35 P34 P33 P32 P31 P30 P57 P56 P55 P54 P53 P52 P51 P50 P65 P64 P63 P62 ...
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Section 1 Overview Classification Abbreviation I/O port PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC3 PC2 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 ...
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Classification Abbreviation I/O port PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PM4 PM3 PM2 PM1 PM0 Pin No. (FP-144LV) I/O Description 11 Input/ ...
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Section 1 Overview Rev.1.00 Jun. 07, 2006 Page 20 of 1102 REJ09B0294-0100 ...
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The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ...
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Section 2 CPU • Two base registers Vector base register Short address base register • 4-Gbyte address space Program: 4 Gbytes Data: 4 Gbytes • High-speed operation All frequently-used instructions executed in one or two ...
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CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. For details on mode settings, see section 3.1, Operating Mode Selection. CPU operating modes 2.2.1 Normal Mode The exception vector table and stack ...
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Section 2 CPU • Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the ...
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Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. • Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program ...
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Section 2 CPU 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. • Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas ...
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Stack Structure The stack structure subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. SP Reserved (a) ...
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Section 2 CPU H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005 H'00000006 H'00000007 Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute ...
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Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch ...
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Section 2 CPU 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register ...
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General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. SP (ER7) 2.5.2 Program Counter (PC) ...
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Condition-Code Register (CCR) CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can ...
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Section 2 CPU Initial Value Bit Bit Name 2 Z Undefined R Undefined R Undefined R/W 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask ...
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Vector Base Register (VBR) VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for ...
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Section 2 CPU 2.6 Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword ...
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Section 2 CPU 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in ...
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Function Instructions Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC 5 Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC [Legend] B: Byte size W: Word size L: Longword size Notes: 1. ...
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Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Classifi- cation Instruction Size Data MOV B/W/L ...
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Classifi- Instruction Size cation Arithmetic MULXS, B/W operations DIVXS MULS, DIVS W/L NEG B W/L EXTU, EXTS W/L TAS B MAC — CLRMAC — LDMAC — STMAC — Logic AND, OR, XOR B operations B B W/L NOT B W/L ...
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Section 2 CPU Classifi- Instruction Size cation Bit BFLD B manipu- BFST B lation 8 Branch BRA/BS, BRA/BC BSR/BS, BSR/BC* B System LDC B/W* control (CCR, EXR) LDC L (VBR, SBR) STC B/W* (CCR, EXR) STC L (VBR, ...
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Table 2.2 Combinations of Instructions and Addressing Modes (2) Classifi- cation Instruction Size — Branch BRA/BS, BRA/BC — BSR/BS, BSR/BC — Bcc — BRA — BRA/S — JMP — BSR — JSR — RTS, RTS/L — System TRAPA control — ...
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Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd ...
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Table 2.4 Data Transfer Instructions Instruction Size Function #IMM → (EAd), (EAs) → (EAd) MOV B/W/L Transfers data between immediate data, general registers, and memory. (EAs) → Rd MOVFPE → (EAs) MOVTPE* B @SP+ → Rn POP W/L ...
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Section 2 CPU Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B B Transfers a data block. EEPMOV.W Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of ...
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Table 2.6 Arithmetic Operation Instructions Instruction Size Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) ADD B/W/L SUB Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted ...
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Section 2 CPU Instruction Size Function Rd ÷ Rs → Rd DIVU W/L Performs unsigned division on data in two general registers: either 16 bits ÷ 16 bits → 16-bit quotient bits ÷ 32 bits → 32-bit quotient. ...
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Table 2.7 Logic Operation Instructions Instruction Size Function (EAd) ∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd) AND B/W/L Performs a logical AND operation on data between immediate data, general registers, and memory. (EAd) ∨ #IMM → (EAd), (EAd) ...
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Section 2 CPU Table 2.9 Bit Manipulation Instructions Instruction Size Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified ...
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Instruction Size Function C ∨ [~ (<bit-No.> of <EAd>)] → C BIOR B ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in ...
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Section 2 CPU Instruction Size Function ∼ Z → (<bit-No.> of <EAd>) BISTZ B Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit ...
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Table 2.11 System Control Instructions Instruction Size Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. RTE/L — Returns from an exception-handling routine, restoring data from the stack to multiple general registers. SLEEP — Causes ...
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Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field ...
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Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode ...
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Section 2 CPU 2.8.2 Register Indirect—@ERn The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In ...
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Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− • Register indirect with post-increment—@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ...
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Section 2 CPU Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. After execution, ER0 is H'00001002. 2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is ...
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Immediate—#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate ...
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Section 2 CPU 2.8.10 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed 8-bit absolute address in ...
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Extended Memory Indirect—@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of ...
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Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. Addressing Mode and Instruction Format 1 Immediate op IMM Register direct Register indirect Register indirect with 16-bit displacement ...
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Table 2.15 Effective Address Calculation for Branch Instructions No. Addressing Mode and Instruction Format Register indirect Program-counter relative with 8-bit displacement 2 op disp Program-counter relative with 16-bit displacement op disp Program-counter relative with index register 3 ...
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Section 2 CPU 2.9 Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. • Reset state In this state ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has five operating modes (modes and 7). The operating mode is selected by the setting of mode pins MD2 to MD0. The setting of mode ...
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Section 3 MCU Operating Modes Mode single-chip initiation mode. In the initial state, all areas are designated to 8-bit access space and all I/O ports can be used as general input/output ports. The external address space cannot ...
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Bit Bit Name Initial Value R/W 15 MDS7 Undefined* MDS3 Undefined* 10 MDS2 Undefined* 9 MDS1 Undefined* 8 MDS0 Undefined* 7 Undefined* ...
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Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode. Bit 15 14 ...
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Initial Value Bit Bit Name 10 Undefined 9 EXPE Undefined 8 RAME 1 All 0 1 DTCMD 1 Notes: 1. For details on instruction fetch mode, see section 2.3, Instruction Fetch. 2. ...
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Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 2 This is the boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash ...
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Mode 6 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is enabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access ...
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Section 3 MCU Operating Modes 3.3.6 Pin Functions Table 3.4 lists the pin functions in each operating mode. Table 3.4 Pin Functions in Each Operating Mode (Advanced Mode) Port Port A PA7 PA6 to PA3 PA2 to PA0 Port B ...
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Address Map 3.4.1 Address Map Figures 3.1 and 3.2 show the address map in each operating mode. (Advanced mode) H'000000 On-chip ROM H'060000 Access prohibited area H'080000 External address space/ reserved area* H'FD9000 Access prohibited area H'FDC000 External address ...
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Section 3 MCU Operating Modes Mode 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 External address space H'FD9000 Access prohibited area H'FDC000 External address space H'FF0000 Access prohibited area H'FF2000 On-chip RAM/ external address 2 space* H'FFC000 External address ...
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Mode 2 Boot mode (Advanced mode) H'000000 On-chip ROM H'080000 External address space/ reserved area* H'FD9000 Access prohibited area H'FDC000 External address space/ reserved area* H'FF0000 Access prohibited area H'FF2000 On-chip RAM* H'FFC000 External address space/ reserved area* H'FFEA00 On-chip ...
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Section 3 MCU Operating Modes Mode 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 External address space H'FD9000 Access prohibited area H'FDC000 External address space H'FF0000 Access prohibited area H'FF2000 On-chip RAM/ external address 2 space* H'FFC000 External address ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal ...
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Section 4 Exception Handling 4.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector ...
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Exception Source Reserved for system use User area (not used) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 Reserved for system use 4 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. ...
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Section 4 Exception Handling Table 4.3 Calculation Method of Exception Handling Vector Table Address Exception Source Calculation Method of Vector Table Address Reset, CPU address error Vector table address = (vector table address offset) Vector table address = VBR + ...
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Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, ...
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Section 4 Exception Handling Bφ RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start ...
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Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared. For ...
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Section 4 Exception Handling 4.5 Address Error 4.5.1 Address Error Source Instruction fetch, stack operation, or data read/write shown in table 4.5 may cause an address error. Table 4.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Instruction ...
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Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents ...
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Section 4 Exception Handling 4.6 Interrupts 4.6.1 Interrupt Sources Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 4.7. Table 4.7 Interrupt Sources Type Source NMI NMI pin (external input) Pins IRQ0 to IRQ11 ...
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Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiple-interrupt control. The source to start interrupt exception ...
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Section 4 Exception Handling Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling Interrupt Control Mode 0 2 [Legend] 1: Set Cleared to 0 : Retains the previous value. 4.7.2 Sleep Instruction Exception Handling ...
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Table 4.9 Status of CCR and EXR after Sleep Instruction Exception Handling Interrupt Control Mode 0 2 [Legend] 1: Set Cleared to 0 : Retains the previous value. 4.7.3 Exception Handling by Illegal Instruction The illegal instructions ...
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Section 4 Exception Handling Table 4.10 Status of CCR and EXR after Illegal Instruction Exception Handling Interrupt Control Mode 0 2 [Legend] 1: Set Cleared to 0 : Retains the previous value. 4.8 Stack Status after Exception ...
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Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer ...
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Section 4 Exception Handling Rev.1.00 Jun. 07, 2006 Page 92 of 1102 REJ09B0294-0100 ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). • Priority can be assigned by the ...
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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTCR NMIEG NMI input NMI input unit IRQ11 to HRQ0 input IRQ input unit TM32K IRQ15 input ISCR Internal interrupt sources Source selector WOVI ...
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Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ11 to IRQ0 Input 5.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) ...
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Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit 7 6 Bit Name Initial Value Initial Value Bit Bit Name ...
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CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DTC and DMAC. The interrupt exception handling by the CPU can be given priority over that of the DTC and DMAC transfer. The ...
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Section 5 Interrupt Controller Initial Value Bit Bit Name 2 CPUP2 0 1 CPUP1 0 0 CPUP0 0 Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. ...
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Initial Bit Bit Name Value IPR14 1 13 IPR13 1 12 IPR12 1 IPR10 1 9 IPR9 1 8 IPR8 1 IPR6 1 5 IPR5 1 4 IPR4 ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value IPR2 1 1 IPR1 1 0 IPR0 1 5.3.4 IRQ Enable Register (IER) IER enables interrupt requests IRQ15, and IRQ11 to IRQ0. Bit 15 14 Bit ...
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Initial Value Bit Bit Name 11 IRQ11E 0 10 IRQ10E 0 9 IRQ9E 0 8 IRQ8E 0 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 IRQ0E ...
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Section 5 Interrupt Controller 5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH and ISCRL select the source that generates an interrupt request from IRQ15, and IRQ11 to IRQ0 input. Upon changing the setting of ISCR, IRQnF (n ...
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ISCRH Initial Bit Bit Name Value 15 IRQ15SR 0 14 IRQ15SF All 0 7 IRQ11SR 0 6 IRQ11SF 0 5 IRQ10SR 0 4 IRQ10SF 0 3 IRQ9SR 0 2 IRQ9SF 0 R/W Description R/W ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 1 IRQ8SR 0 0 IRQ8SF 0 • ISCRL Initial Bit Bit Name Value 15 IRQ7SR 0 14 IRQ7SF 0 13 IRQ6SR 0 12 IRQ6SF 0 11 IRQ5SR 0 10 IRQ5SF 0 ...
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Initial Bit Bit Name Value 9 IRQ4SR 0 8 IRQ4SF 0 7 IRQ3SR 0 6 IRQ3SF 0 5 IRQ2SR 0 4 IRQ2SF 0 3 IRQ1SR 0 2 IRQ1SF 0 1 IRQ0SR 0 0 IRQ0SF 0 R/W Description R/W IRQ4 Sense ...
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Section 5 Interrupt Controller 5.3.6 IRQ Status Register (ISR) ISR is an IRQ15, and IRQ11 to IRQ0 interrupt request register. Bit 15 14 Bit Name IRQ15F Initial Value 0 0 R/W R/(W)* R/W Bit 7 6 Bit Name IRQ7F ...
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Initial Value Bit Bit Name 11 IRQ11F 0 10 IRQ10F 0 9 IRQ9F 0 8 IRQ8F 0 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 IRQ1F 0 0 IRQ0F ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 15 SSI15 0 All 0 11 SSI11 0 10 SSI10 0 9 SSI9 0 8 SSI8 0 7 SSI7 0 6 SSI6 0 5 SSI5 0 4 ...
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Interrupt Sources 5.4.1 External Interrupts There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always ...
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Section 5 Interrupt Controller Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, and P5ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the ...
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Interrupt Exception Handling Vector Table Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, ...
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Section 5 Interrupt Controller Classification Interrupt Source Reserved for system use Refresh CMI controller Reserved for system use A/D ADI Reserved for system use TPU_0 TGI0A TGI0B TGI0C TGI0D TCI0V TPU_1 TGI1A TGI1B TCI1V TCI1U TPU_2 TGI2A ...
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Classification Interrupt Source TPU_5 TGI5A TGI5B TCI5V TCI5U Reserved for system use TMR_0 CMI0A CMI0B OV0I TMR_1 CMI1A CMI1B OV1I TMR_2 CMI2A CMI2B OV2I TMR_3 CMI3A CMI3B OV3I DMAC DMTEND0 DMTEND1 DMTEND2 DMTEND3 Reserved for system use DMAC ...
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Section 5 Interrupt Controller Classification Interrupt Source Reserved for system use SCI_0 ERI0 RXI0 TXI0 TEI0 SCI_1 ERI1 RXI1 TXI1 TEI1 SCI_2 ERI2 RXI2 TXI2 TEI2 Reserved for system use SCI_4 ERI4 RXI4 TXI4 TEI4 Reserved for ...
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Classification Interrupt Source IIC2 IICI0 Reserved for system use IICI1 Reserved for system use SCI_5 RXI5 TXI5 ERI5 TEI5 SCI_6 RXI6 TXI6 ERI6 TEI6 TMR_4 CMIA4 or CMIB4 228 TMR_5 CMIA5 or CMIB5 229 TMR_6 CMIA6 or CMIB6 230 TMR_7 ...
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Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control ...
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The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure 5.3 Flowchart of Procedure ...
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Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level ( bits) in EXR of the CPU and the IPR setting. ...
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Program execution state Interrupt generated? Yes No Level 7 interrupt? Yes Level 6 interrupt? No Mask level 6 or below? Yes Mask level 5 Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address ...
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Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area ...
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Interrupt Response Times Table 5.4 shows interrupt response times – the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 5.4 are ...
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Section 5 Interrupt Controller Table 5.5 Number of Execution States in Interrupt Handling Routine On-Chip Symbol Memory Vector fetch Instruction fetch Stack manipulation [Legend] m: Number of wait cycles in an ...
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Interrupt request On-chip peripheral Interrupt request module clear signal Interrupt request IRQ Interrupt request clear signal interrupt Interrupt controller Figure 5.6 Block Diagram of DTC, DMAC, and Interrupt Controller (1) Selection of Interrupt Sources The activation source for each DMAC ...
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Section 5 Interrupt Controller (2) Priority Determination The DTC activation source is selected according to the default priority, and the selection is not affected by its mask level or priority level. For respective priority levels, see table 8.1, Interrupt Sources, ...
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CPU Priority Control Function Over DTC and DMAC The interrupt controller has a function to control the priority among the DTC, DMAC, and the CPU by assigning different priority levels to the DTC, DMAC, and CPU. Since the priority ...
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Section 5 Interrupt Controller The priority level which is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. In interrupt control mode 0, the I bit in CCR of the CPU is reflected in ...
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Table 5.8 shows a setting example of the priority control function over the DTC and DMAC and the transfer request control state. A priority level can be independently set to each DMAC channel, but the table only shows one channel ...
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Section 5 Interrupt Controller 5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable ...
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Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the ...
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Section 5 Interrupt Controller 5.8.6 Interrupts of Peripheral Modules To clear an interrupt source flag by the CPU using an interrupt function of a peripheral module, the flag must be read from after clearing within the interrupt processing routine. This ...
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Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus ...
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Section 6 Bus Controller (BSC) • DRAM interface DRAM interface is available as area 2 Row/column address-multiplexed output ( bits) Two CAS signals control byte accesses for 16-bit data bus device CAS assertion period can be ...
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A block diagram of the bus controller is shown in figure 6.1. CPU address bus DMAC address bus DTC address bus Internal bus control signals CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal CPU bus request ...
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Section 6 Bus Controller (BSC) 6.2 Register Descriptions The bus controller has the following registers. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register A (WTCRA) • Wait control register B (WTCRB) • ...
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Bus Width Control Register (ABWCR) ABWCR specifies the data bus width for each area in the external address space. Bit 15 14 Bit Name ABWH7 ABWH6 Initial Value 1 1 R/W R/W R/W Bit 7 6 Bit Name ABWL7 ...
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Section 6 Bus Controller (BSC) 6.2.2 Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space and enables/disables wait cycle insertion. Bit 15 14 Bit Name AST7 ...
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Wait Control Registers A and B (WTCRA, WTCRB) WTCRA and WTCRB select the number of program wait cycles for each area in the external address space. • WTCRA Bit 15 14 Bit Name W72 Initial Value 0 1 ...
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Section 6 Bus Controller (BSC) • WTCRA Initial Bit Bit Name Value W72 1 13 W71 1 12 W70 1 W62 1 9 W61 1 8 W60 1 Rev.1.00 ...
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Initial Value Bit Bit Name 6 W52 1 5 W51 1 4 W50 1 W42 1 1 W41 1 0 W40 1 • WTCRB Initial Bit Bit Name Value R/W Description R/W Area ...
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Section 6 Bus Controller (BSC) Initial Bit Bit Name Value 14 W32 1 13 W31 1 12 W30 1 W22 1 9 W21 1 8 W20 1 Rev.1.00 Jun. 07, 2006 Page 140 of 1102 REJ09B0294-0100 ...
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Initial Value Bit Bit Name W12 1 5 W11 1 4 W10 1 W02 1 1 W01 1 0 W00 1 R/W Description R Reserved This is a read-only bit and cannot ...
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Section 6 Bus Controller (BSC) 6.2.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the negation timing of the read strobe signal (RD) when reading the external address spaces specified as a basic bus interface or the address/data multiplexed I/O ...
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Bφ RD RDNn = 0 Data RD RDNn = 1 Data Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) CS Assertion Period Control Registers (CSACR) 6.2.5 CSACR selects whether or not the assertion periods of the chip ...
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Section 6 Bus Controller (BSC) Initial Value Bit Bit Name 15 CSXH7 0 14 CSXH6 0 13 CSXH5 0 12 CSXH4 0 11 CSXH3 0 10 CSXH2 0 9 CSXH1 0 8 CSXH0 0 7 CSXT7 0 6 CSXT6 0 ...
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T Bφ Address CSn AS BS RD/WR RD Read Data bus LHWR, LLWR Write Data bus Figure 6.3 CS and Address Assertion Period Extension (Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0) Bus cycle T T ...
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Section 6 Bus Controller (BSC) 6.2.6 Idle Control Register (IDLCR) IDLCR specifies the idle cycle insertion conditions and the number of idle cycles. Bit 15 14 Bit Name IDLS3 IDLS2 Initial Value 1 1 R/W R/W R/W Bit 7 6 ...