DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 535
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
DF2398F20V
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DF2398F20V
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14.3.4
In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for
high-speed serial communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a
common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or
written during transmission or reception, enabling continuous data transfer.
Figure 14-14 shows the general format for clocked synchronous serial communication.
In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial
clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock.
In clocked serial communication, one character consists of data output starting with the LSB and ending with the MSB.
After the MSB is output, the transmission line holds the MSB state.
In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock.
Data Transfer Format: A fixed 8-bit data format is used.
No parity or multiprocessor bits are added.
Clock: Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK
pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of
SCI clock source selection, see table 14-9.
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed
high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the
RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external
clock as the clock source.
Operation in Clocked Synchronous Mode
Note: * High except in continuous transfer
Serial
Serial
clock
data
Don’t care
Figure 14-14 Data Format in Synchronous Communication
*
LSB
Bit 0
Bit 1
One unit of transfer data (character or frame)
Bit 2
Bit 3
Bit 4
Bit 5
Rev.6.00 Oct.28.2004 page 505 of 1016
Bit 6
MSB
Bit 7
Don’t care
*
REJ09B0138-0600H
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