DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 503

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error
interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is
set to 1.
Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Notes: 1. The TDRE flag in SSR is fixed at 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is
only valid in asynchronous mode when the MP bit in SMR is set to 1.
ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is
2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is
cleared to 0.
SMR setting must be performed to decide the transfer format before setting the TE bit to 1.
detected in clocked synchronous mode.
SMR setting must be performed to decide the transfer format before setting the RE bit to 1.
Bit 6
RIE
0
1
Bit 5
TE
0
1
Bit 4
RE
0
1
Description
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
disabled*
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
enabled
Description
Transmission disabled*
Transmission enabled*
Description
Reception disabled*
Reception enabled*
2
1
2
1
Rev.6.00 Oct.28.2004 page 473 of 1016
(Initial value)
(Initial value)
(Initial value)
REJ09B0138-0600H