DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 414
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
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The correspondence between PWM output pins and registers is shown in table 10-7.
Table 10-7 PWM Output Registers and Output Pins
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Rev.6.00 Oct.28.2004 page 384 of 1016
REJ09B0138-0600H
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD.
The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at
compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at
compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired
TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in
TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare
match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are
identical, the output value does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation.
Channel
0
1
2
3
4
5
Registers
TGR0A
TGR0B
TGR0C
TGR0D
TGR1A
TGR1B
TGR2A
TGR2B
TGR3A
TGR3B
TGR3C
TGR3D
TGR4A
TGR4B
TGR5A
TGR5B
PWM Mode 1
TIOCA0
TIOCC0
TIOCA1
TIOCA2
TIOCA3
TIOCC3
TIOCA4
TIOCA5
Output Pins
PWM Mode 2
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
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