DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 222
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.4.2
DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A
port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit.
DMATCR is initialized to H'00 by a reset, and in standby mode.
Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 0.
Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output.
Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output.
The TEND pins are assigned only to channel B in short address mode.
The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer
source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the
block counter reached 0.
Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 0.
Rev.6.00 Oct.28.2004 page 192 of 1016
REJ09B0138-0600H
Bit
DMATCR :
Initial value :
R/W
DMA Terminal Control Register (DMATCR)
Bit 5
TEE1
0
1
Bit 4
TEE0
0
1
:
:
—
—
7
0
Description
TEND1 pin output disabled
TEND1 pin output enabled
Description
TEND0 pin output disabled
TEND0 pin output enabled
—
—
6
0
TEE1
R/W
5
0
TEE0
R/W
4
0
—
—
3
0
—
—
2
0
—
—
1
0
—
—
0
0
(Initial value)
(Initial value)
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