M30281F6HP#U9B Renesas Electronics America, M30281F6HP#U9B Datasheet - Page 388
M30281F6HP#U9B
Manufacturer Part Number
M30281F6HP#U9B
Description
IC M16C/28 MCU FLASH 48K 64LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30281F6HP#U9B
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30281F6HP#U9BM30281F6HP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30281F6HP#U9BM30281F6HP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 20.1 Uses of IT Bit in the G1BCR0 Register and G1BTRR Register
J
6
1
0
0
20.7.2 Rewrite the ICOCiIC Register
20.7.3 Waveform Generating Function
20.7.4 IC/OC Base Timer Interrupt
C
2
b (
9
b (
2 /
When the interrupt request to the ICOCiIC register is generated during the instruction process, the IR bit
may not be set to "1" (interrupt requested) and the interrupt request may not be acknowledged. At that
time, when the bit in the G1IR register is held to "1" (interrupt requested), the following IC/OC interrupt
request will not be generated. When changing the ICOCiIC register settiing, use the following instruction.
When initializing Timer S, change the ICOCiIC register setting with the request again after setting the
IOCiIC and G1IR registers to "00
1. If the BTS bit in the G1BCR1 register is set to "0" (base timer is reset) when the waveform is generating
and the base timer is stopped counting, the waveform output pin keeps the same output level. The output
level will be changed when the base timer and the G1POj register match the setting value next time after
the base timer starts counting again.
2. If the G1POCRj register is set when the waveform is generated, the same setting value of the IVL bit is
applied to the waveform generating pin. Do not set the G1POCRj register when the waveform is generat-
ing.
3. When the RST1 bit in the G1BCR1 register is set to "1" (the base timer is reset by matching the G1PO0
If the MCU is operated in the combination selected from Tabl e 1 for use when the RST4 bit in the
G1BCR0 register is set to 1 (reset the base timer that matches the G1BTRR register) to reset the base
timer, an IC/OC base timer interrupt request is generated twice.
The second IC/OC base timer interrupt request is generated because the base timer overflow request is
generated after one fBT1 clock cycle as soon as the base timer is reset.
One of the following conditions must be met in order not to generate the IC/OC base timer interrupt
request twice:
1) When the RST4 bit is set to 1, set the G1BTRR register with a combination other than what is listed in
2) Do not reset the base timer by matching the G1BTRR register. Reset the base timer by matching the
0 .
B
t i
t i
0
0
register), the base timer is reset after two clock cycles of f
G1PO0 register value. A high-level ("H") signal is applied to the OUTC10 pin between the base timer
value match to the base timer reset.
8
1
1
Table 20.1.
G1P00 register. In other words, do not set the RST4 bit to 1 to reset the base timer. Set the RST1 bit in
the G1BCR1 register to 1 (reset the base timer that matches the G1P00 register).
0
Subject instructions: AND, OR, BCLR, BSET
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page 366
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when the base timer value matches the
20. Precautions
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