M30281F6HP#U9B Renesas Electronics America, M30281F6HP#U9B Datasheet - Page 103
M30281F6HP#U9B
Manufacturer Part Number
M30281F6HP#U9B
Description
IC M16C/28 MCU FLASH 48K 64LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30281F6HP#U9B
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30281F6HP#U9BM30281F6HP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30281F6HP#U9BM30281F6HP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
R
R
e
E
1
. v
Figure 9.10 Interrupts Priority Select Circuit
J
6
0
C
2
9
2 /
0 .
B
0
0
8
0
G
4
J
7
a
o r
0 -
. n
u
2
3
p
0
, 1
IC/OC interrupt 1, I
0
(
Priority level of each interrupt
M
UART2 transmission, NACK2
2
IC/OC base timer, S
0
1
UART2 reception, ACK2
re-oscillation detection
0
6
Low voltage detection
UART 2 bus collision
UART1 transmission
UART0 transmission
Oscillation stop and
7
Key input interrupt
C
IC/OC interrupt 0
UART1 reception
UART0 reception
A/D conversion
Watchdog timer
Address match
2 /
SI/O4, INT5
SI/O3, INT4
Timer B2
Timer B0
Timer A3
Timer A1
Timer B1
Timer A4
Timer A2
Timer A0
, 8
DMA0
DMA1
INT1
INT3
INT2
INT0
I flag
DBC
IPL
NMI
page 81
M
2
C bus interface
1
6
CL
C
/S
2 /
f o
DA
8
3
) B
8
5
Level 0 (initial value)
Lowest
Priority of peripheral function interrupts
(if priority levels are same)
Highest
Interrupt request level resolution output to clock
generation circuit (Figure 7.1)
accepted
Interrupt
request
9. Interrupts
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