MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 17

IC MCU 176 BYTES RAM 28-SOIC

MC705P6ACDWE

Manufacturer Part Number
MC705P6ACDWE
Description
IC MCU 176 BYTES RAM 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC705P6ACDWE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC705P
Core
HC05
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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0
1.3.8 TCMP
This pin is the output from the 16-bit timer’s output compare function. It is low after reset. Refer to
Chapter 8 Capture/Compare
1.3.9 IRQ/V
This input pin drives the asynchronous interrupt function of the MCU in user mode and provides the V
programming voltage in bootloader mode. The MCU will complete the current instruction being executed
before it responds to the IRQ interrupt request. When the IRQ/V
internally to signify an interrupt has been requested. When the MCU completes its current instruction, the
interrupt latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU will begin the interrupt sequence.
Depending on the MOR LEVEL bit, the IRQ/V
the IRQ/V
be held low for at least one t
set), the IRQ/V
IRQ/V
internal Schmitt trigger to improve noise immunity. Refer to
Freescale Semiconductor
PP
pin is not used, it must be tied to the V
PP
pin and/or while the IRQ/V
PP
If the voltage level applied to the IRQ/V
the MCU’s mode of operation. See
PP
(Maskable Interrupt Request)
input pin requires an external resistor connected to V
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
ILIH
Timer.
time period. If the edge- and level-sensitive mode is selected (LEVEL bit
PP
pin is held in the low state. In either case, the IRQ/V
PP
DD
pin will trigger an interrupt on either a negative edge at
NOTE
Chapter 3 Operating
supply. The IRQ/V
PP
pin exceeds V
Chapter 5
PP
pin is driven low, the event is latched
PP
Interrupts.
DD
DD
Modes.
pin input circuitry contains an
, it may affect
for wired-OR operation. If the
Functional Pin Description
PP
pin must
PP
17