MC908QY8CDWE Freescale Semiconductor, MC908QY8CDWE Datasheet - Page 91

IC MCU 8BIT 8K FLASH 16-SOIC

MC908QY8CDWE

Manufacturer Part Number
MC908QY8CDWE
Description
IC MCU 8BIT 8K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QY8CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QY
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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10.4 LVI Interrupts
The LVI module does not generate interrupt requests.
10.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.5.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.5.2 Stop Mode
If the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active. If enabled to generate resets, the LVI module can generate
a reset and bring the MCU out of stop mode.
10.6 Registers
The LVI status register (LVISR) contains a status bit that is useful when the LVI is enabled and LVI reset
is disabled.
LVIOUT — LVI Output Bit
Freescale Semiconductor
This read-only flag becomes set when the V
when V
DD
voltage rises above V
Reset:
Read:
Write:
LVIOUT
Bit 7
0
= Unimplemented
Figure 10-2. LVI Status Register (LVISR)
V
TRIPF
6
0
0
V
Table 10-1. LVIOUT Bit Indication
V
TRIPR
DD
DD
MC68HC908QB8 Data Sheet, Rev. 3
< V
V
> V
< V
DD
DD
. (See
TRIPR
TRIPF
5
0
0
< V
TRIPR
DD
Table
voltage falls below the V
4
0
0
10-1).
Previous value
R
3
0
0
LVIOUT
0
1
= Reserved
2
0
0
TRIPF
1
0
0
trip voltage and is cleared
Bit 0
R
0
LVI Interrupts
91

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