MC908QY8CDWE Freescale Semiconductor, MC908QY8CDWE Datasheet - Page 81

• Manufacturer Part Number: MC908QY8CDWE
• Description: IC MCU 8BIT 8K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY8CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: HC08QY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.8 Registers
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
IRQF — IRQ Flag Bit
ACK — IRQ Interrupt Request Acknowledge Bit
IMASK — IRQ Interrupt Mask Bit
MODE — IRQ Edge/Level Select Bit
Freescale Semiconductor
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This read-only status bit is set when the IRQ interrupt is pending.
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads 0.
Writing a 1 to this read/write bit disables the IRQ interrupt request.
This read/write bit controls the triggering sensitivity of the IRQ pin.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
1 = IRQ interrupt request disabled
0 = IRQ interrupt request enabled
1 = IRQ interrupt request on falling edges and low levels
0 = IRQ interrupt request on falling edges only
Shows the state of the IRQ flag
Clears the IRQ latch
Masks the IRQ interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
Reset:
Read:
Write:
Bit 7
0
0
Figure 8-3. IRQ Status and Control Register (INTSCR)
= Unimplemented
6
0
0
MC68HC908QB8 Data Sheet, Rev. 3
5
0
0
0
0
4
IRQF
3
0
ACK
2
0
0
IMASK
1
0
MODE
Bit 0
0
Registers
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