MC908QY8CDWE Freescale Semiconductor, MC908QY8CDWE Datasheet - Page 172

IC MCU 8BIT 8K FLASH 16-SOIC

MC908QY8CDWE

Manufacturer Part Number
MC908QY8CDWE
Description
IC MCU 8BIT 8K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QY8CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QY
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Serial Peripheral Interface (SPI) Module
SPTIE— SPI Transmit Interrupt Enable
15.8.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these conditions:
The SPI status and control register also contains bits that perform these functions:
SPRF — SPI Receiver Full Bit
ERRIE — Error Interrupt Enable Bit
OVRF — Overflow Bit
172
This read/write bit enables interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register.
This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF interrupt, user software can clear SPRF by reading the SPI status and control register
with SPRF set followed by a read of the SPI data register.
This read/write bit enables the MODF and OVRF bits to generate interrupt requests.
This clearable, read-only flag is set if software does not read the byte in the receive data register before
the next full byte enters the shift register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the receive data register.
1 = SPTE interrupt requests enabled
0 = SPTE interrupt requests disabled
1 = Receive data register full
0 = Receive data register not full
1 = MODF and OVRF can generate interrupt requests
0 = MODF and OVRF cannot generate interrupt requests
1 = Overflow
0 = No overflow
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow error)
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
Reset:
Read:
Write:
SPRF
Bit 7
Figure 15-14. SPI Status and Control Register (SPSCR)
0
= Unimplemented
ERRIE
6
0
MC68HC908QB8 Data Sheet, Rev. 3
OVRF
5
0
MODF
0
4
SPTE
3
1
MODFEN
2
0
SPR1
1
0
Freescale Semiconductor
SPR0
Bit 0
0

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