MC908QY8CDWE Freescale Semiconductor, MC908QY8CDWE Datasheet - Page 130

IC MCU 8BIT 8K FLASH 16-SOIC

MC908QY8CDWE

Manufacturer Part Number
MC908QY8CDWE
Description
IC MCU 8BIT 8K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QY8CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QY
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908QY8CDWE
Manufacturer:
Winbond
Quantity:
16 700
Part Number:
MC908QY8CDWE
Manufacturer:
FREESCALE
Quantity:
20 000
Enhanced Serial Communications Interface (ESCI) Module
13.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
LINT — LIN Transmit Enable
LINR — LIN Receiver Bits
130
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in
In LIN (version 1.2 and later) systems, the master node transmits a break character which will appear
as 11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
slave node must be within ±15% of the master node's oscillator. Because a slave node cannot know
if it is running faster or slower than the master node (prior to synchronization), the LINR bit allows the
slave node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits.
The break symbol length must be verified in software in any case, but the LINR bit serves as a filter,
preventing false detections of break characters that are really 0x00 data characters.
Reset:
Read:
Write:
There are two prescalers available to adjust the baud rate — one in the
ESCI baud rate register and one in the ESCI prescaler register.
Table
Table
LINT
0
0
0
1
1
1
1
13-5.
13-5.
LINT
Bit 7
R
0
LINR
0
1
1
0
0
1
1
Figure 13-16. ESCI Baud Rate Register (SCBR)
= Reserved
LINR
6
0
M
Table 13-5. ESCI LIN Control Bits
X
0
1
0
1
0
1
MC68HC908QB8 Data Sheet, Rev. 3
SCP1
Normal ESCI functionality
11-bit break detect enabled for LIN receiver
12-bit break detect enabled for LIN receiver
13-bit generation enabled for LIN transmitter
14-bit generation enabled for LIN transmitter
11-bit break detect/13-bit generation enabled for LIN
12-bit break detect/14-bit generation enabled for LIN
5
0
SCP0
NOTE
0
4
Functionality
3
R
0
SCR2
2
0
SCR1
1
0
Freescale Semiconductor
SCR0
Bit 0
0

Related parts for MC908QY8CDWE