MC908QY8CDWE Freescale Semiconductor, MC908QY8CDWE Datasheet - Page 123

IC MCU 8BIT 8K FLASH 16-SOIC

MC908QY8CDWE

Manufacturer Part Number
MC908QY8CDWE
Description
IC MCU 8BIT 8K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908QY8CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QY
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
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MC908QY8CDWE
Manufacturer:
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Part Number:
MC908QY8CDWE
Manufacturer:
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WAKE — Wakeup Condition Bit
ILTY — Idle Line Type Bit
PEN — Parity Enable Bit
PTY — Parity Bit
13.8.2 ESCI Control Register 2
ESCI control register 2 (SCC2):
Freescale Semiconductor
This read/write bit determines which condition wakes up the ESCI: a 1 (address mark) in the MSB
position of a received character or an idle condition on the RxD pin.
This read/write bit determines when the ESCI starts counting 1s as idle character bits. The counting
begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string
of 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after
the stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
This read/write bit enables the ESCI parity function (see
function inserts a parity bit in the MSB position (see
This read/write bit determines whether the ESCI generates and checks for odd parity or even parity
(see
1 = Address mark wakeup
0 = Idle line wakeup
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
1 = Parity function enabled
0 = Parity function disabled
1 = Odd parity
0 = Even parity
Enables these interrupt requests:
Enables the transmitter
Table
SCTE bit to generate transmitter interrupt requests
TC bit to generate transmitter interrupt requests
SCRF bit to generate receiver interrupt requests
IDLE bit to generate receiver interrupt requests
M
0
1
0
0
1
1
13-4).
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Control Bits
PEN:PTY
0 X
0 X
1 0
1 1
1 0
1 1
Table 13-4. Character Format Selection
Start Bits
1
1
1
1
1
1
MC68HC908QB8 Data Sheet, Rev. 3
Data Bits
8
9
7
7
8
8
NOTE
Character Format
Parity
None
None
Table
Even
Even
Odd
Odd
Table
13-2).
Stop Bits
13-4). When enabled, the parity
1
1
1
1
1
1
Character Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
Registers
123

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