ST72F325K4T6 STMicroelectronics, ST72F325K4T6 Datasheet
ST72F325K4T6
Specifications of ST72F325K4T6
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ST72F325K4T6 Summary of contents
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MCU with 16 to 60K Flash/ROM, ADC, CSS, Features Memories ■ – 16K to 60K dual voltage High Density Flash (HDFlash 32K ROM with read-out protection capability. In-Application Program- ming and In-Circuit Programming for HDFlash devices ...
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DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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DESCRIPTION The ST72F325 Flash and ST72325 ROM devices are members of the ST7 microcontroller family de- signed for mid-range applications. They are derivatives of the ST72321 and ST72324 devices, with enhanced characteristics and robust Clock Security System. All devices ...
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ST72325xx 2 PIN DESCRIPTION Figure 2. 64-Pin LQFP 14x14 and 10x10 Package Pinout (HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / (HS) PB4 ARTIC1 / PB5 ...
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Figure 3. 48-Pin LQFP 7x7 Device Pinout (HS) PE4 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / (HS) PB4 ARTIC1 / PB5 AIN0 / PD0 AIN1 / PD1 AIN3 / PD2 AIN4 / PD3 ...
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ST72325xx Figure 4. 44/42-Pin LQFP Package Pinouts RDI / PE1 PB0 PB1 PB2 PB3 (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 ...
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Figure 5. 32-Pin LQFP/DIP Package Pinouts MCO / AIN8 / PF0 BEEP / (HS) PF1 OCMP1_A / AIN10 / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 MCO / AIN8 / PF0 BEEP / ...
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ST72325xx PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 142. Legend / Abbreviations for Table 2 Type input output supply Input level Dedicated analog input ...
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Pin n° Pin Name PD4/AIN4 PD5/AIN5 PD6/AIN6 PD7/AIN7 AREF 6) 22 ...
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ST72325xx Pin n° Pin Name PC7/SS/AIN15 PA0 PA1 PA2 PA3 (HS ...
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Table 3. LQFP32/DIP32 Device Pin Description Pin n° Pin Name AREF SSA 3 6 PF0/MCO/AIN8 I PF1 (HS)/BEEP I/O C PF4/OCMP1_A I/O C AIN10 6 ...
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ST72325xx Pin n° Pin Name 28 31 PB0/PWM3 I PB3/PWM0 I PB4 (HS)/ARTCLK I PD0/AIN0 I PD1/AIN1 I/O C Notes for Table 2 and Table 1. In the ...
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REGISTER & MEMORY MAP As shown in Figure 6, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations 2Kbytes of RAM ...
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ST72325xx Table 4. Hardware Register Map Register Address Block 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h PBDR 0004h Port B PBDDR 0005h PBOR 0006h PCDR 0007h Port C PCDDR 0008h PCOR 0009h PDDR 000Ah Port D PDDDR 000Bh ...
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Register Address Block Label 002Ch MCCSR MCC 002Dh MCCBCR 002Eh to 0030h 0031h TACR2 0032h TACR1 0033h TACSR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch TAIC2HR 003Dh TAIC2LR ...
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ST72325xx Register Address Block 0058h DMCR 0059h DMSR 005Ah DMBK1H 3) DM 005Bh DMBK1L 005Ch DMBK2H 005Dh DMBK2L 005Eh to 006Fh 0070h ADCCSR 0071h ADC ADCDRH 0072h ADCDRL 0073h PWMDCR3 0074h PWMDCR2 0075h PWMDCR1 0076h PWMDCR0 0077h PWMCR 0078h PWM ...
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FLASH PROGRAM MEMORY 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a Byte-by-Byte ba- sis using ...
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ST72325xx FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC Interface ICC needs a minimum of 4 and pins to be connected to the programming tool (see These pins are: – RESET: device reset – device power supply ...
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... Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the spe- cific microcontroller device, the user needs only to implement the ICP hardware interface on the ap- ...
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ST72325xx 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES Enable executing 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 ...
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CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. ...
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ST72325xx CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next ...
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SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. An overview is ...
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ST72325xx 6.2 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by three different source types coming from the multi- oscillator block: an external source ■ 4 crystal or ceramic resonator oscillators ■ an internal high frequency RC ...
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RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ These sources act on ...
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ST72325xx RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteris- tics section. If the ...
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SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD) Auxiliary Voltage Detector (AVD) functions and Clock Security Sys- tem (CSS managed by the SICSR register. 6.4.1 Low Voltage Detector (LVD) The ...
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ST72325xx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply or the external EVD pin voltage level (V ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2.2 Monitoring a Voltage on the EVD pin This mode is selected by setting the AVDS bit in the SICSR register. The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register ...
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ST72325xx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.3 Clock Security System (CSS) The Clock Security System (CSS) protects the ST7 against breakdowns, spikes and overfrequen- cies occurring on the main clock source (f is based on a clock filter and a clock ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.5 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 000x 000x (00h) 7 AVD AVD AVD LVD Bit 7 = AVDS Voltage Detection selection This bit is set ...
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ST72325xx 7 INTERRUPTS 7.1 INTRODUCTION The ST7 enhanced interrupt management pro- vides the following features: Hardware interrupts ■ Software interrupt (TRAP) ■ Nested or concurrent interrupt management ■ with flexible interrupt priority management: – software programmable nesting ...
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INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if ...
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ST72325xx INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see ...
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INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft- ...
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ST72325xx INTERRUPTS (Cont’d) Table 8. Dedicated Interrupt Instruction Set Instruction New Description HALT Entering Halt mode IRET Interrupt routine return JRM Jump if I1:0=11 (level 3) JRNM Jump if I1:0<>11 POP CC Pop CC from the Stack RIM Enable interrupt ...
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INTERRUPTS (Cont’d) Table 9. Interrupt Mapping Source N° Block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt MCC/RTC/ Main clock controller time base interrupt 1 CSS Safe oscillator activation interrupt 2 ei0 External interrupt port A3..0 3 ...
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ST72325xx INTERRUPTS (Cont’d) Figure 25. External Interrupt Control bits PORT A3 INTERRUPT PAOR.3 PADDR.3 PA3 IPA BIT PORT F [2:0] INTERRUPTS PFOR.2 PFDDR.2 PF2 PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 PB3 IPB BIT PORT B4 INTERRUPT PBOR.4 PBDDR.4 PB4 42/197 ...
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EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 IPB IS21 IS20 Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external ...
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ST72325xx INTERRUPTS (Cont’d) Table 10. Nested Interrupts Register Map and Reset Values Address Register 7 (Hex.) Label 0024h ISPR0 I1_3 Reset Value 1 0025h ISPR1 I1_7 1 Reset Value 0026h ISPR2 I1_11 1 Reset Value 0027h ISPR3 Reset Value 1 ...
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POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 26): SLOW, WAIT (SLOW WAIT), AC- ...
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ST72325xx POWER SAVING MODES (Cont’d) 8.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During ...
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POWER SAVING MODES (Cont’d) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two low- est power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruc- tion. The decision to enter either in ...
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ST72325xx POWER SAVING MODES (Cont’d) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) ...
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POWER SAVING MODES (Cont’d) 8.4.2.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O ...
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ST72325xx 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An ...
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I/O PORTS (Cont’d) Figure 33. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( Table 11. I/O Port Mode ...
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ST72325xx I/O PORTS (Cont’d) Table 12. I/O Port Configurations NOT IMPLEMENTED TRUE OPEN DRAIN I/O PORTS R PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V DD I/O ...
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I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ...
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ST72325xx I/O PORTS (Cont’d) 9.5.1 I/O Port Implementation The I/O port register configurations are summa- rised as follows. Standard Ports PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3, MODE floating input pull-up input open drain output push-pull output Interrupt Ports PA2:0, PB6:5, ...
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I/O PORTS (Cont’d) Table 14. I/O Port Register Map and Reset Values Address Register 7 (Hex.) Label Reset Value 0 of all I/O port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 0003h PBDR 0004h PBDDR MSB 0005h PBOR 0006h ...
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ST72325xx 10 ON-CHIP PERIPHERALS 10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application ...
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WATCHDOG TIMER (Cont’d) 10.1.4 How to Program the Watchdog Timeout Figure 2 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milli- seconds. This can be used ...
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ST72325xx WATCHDOG TIMER (Cont’d) Figure 37. Exact Timeout Duration (t WHERE (LSB + 128 min0 OSC2 t = 16384 x t max0 OSC2 t = 125ns MHz OSC2 OSC2 CNT = ...
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WATCHDOG TIMER (Cont’d) 10.1.5 Low Power Modes Mode Description SLOW No effect on Watchdog. WAIT No effect on Watchdog. OIE bit in WDGHALT bit MCCSR in Option register Byte 0 HALT 0 1 10.1.6 Hardware Watchdog Option If Hardware Watchdog ...
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ST72325xx Table 15. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 002Ah Reset Value 0 60/197 ...
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) The Main Clock Controller consists of three differ- ent functions: a programmable CPU clock prescaler ■ a clock-out signal to supply external devices ■ a real time clock timer ...
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ST72325xx MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) 10.2.5 Low Power Modes Mode Description No effect on MCC/RTC peripheral. WAIT MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit is ACTIVE- ...
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the ...
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ST72325xx 10.3 PWM AUTO-RELOAD TIMER (ART) 10.3.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes: ...
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ON-CHIP PERIPHERALS (Cont’d) 10.3.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal possible to read or write the ...
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ST72325xx ON-CHIP PERIPHERALS (Cont’d) Independent PWM signal generation This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode. Each ...
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ON-CHIP PERIPHERALS (Cont’d) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generat the overflow interrupt enable bit, OIE, in the ARTCSR register, is ...
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ST72325xx ON-CHIP PERIPHERALS (Cont’d) Input capture function This mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can generate an interrupt inde- pendently on a selected input signal transition. This event is flagged by ...
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ON-CHIP PERIPHERALS (Cont’d) 10.3.3 Register Description CONTROL / STATUS REGISTER (ARTCSR) Read/Write Reset Value: 0000 0000 (00h) 7 EXCL CC2 CC1 CC0 TCE Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the ...
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ST72325xx ON-CHIP PERIPHERALS (Cont’d) PWM CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) 7 OE3 OE2 OE1 OE0 OP3 Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the ...
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ON-CHIP PERIPHERALS (Cont’d) INPUT CAPTURE CONTROL / STATUS REGISTER (ARTICCSR) Read/Write Reset Value: 0000 0000 (00h CS2 CS1 CIE2 Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set ...
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ST72325xx PWM AUTO-RELOAD TIMER (Cont’d) Table 17. PWM Auto-Reload Timer Register Map and Reset Values Address Register 7 Label (Hex.) PWMDCR3 DC7 0073h 0 Reset Value PWMDCR2 DC7 0074h 0 Reset Value PWMDCR1 DC7 0075h 0 Reset Value PWMDCR0 DC7 ...
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TIMER 10.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals (input capture) ...
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ST72325xx 16-BIT TIMER (Cont’d) Figure 45. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 (See note) ...
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TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read At t0 +Δt LS Byte value ...
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ST72325xx 16-BIT TIMER (Cont’d) Figure 46. Counter Timing Diagram, Internal Clock Divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 47. Counter Timing Diagram, Internal Clock Divided by 4 CPU CLOCK INTERNAL RESET ...
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TIMER (Cont’d) 10.4.3.3 Input Capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to ...
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ST72325xx 16-BIT TIMER (Cont’d) Figure 49. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 50. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ...
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TIMER (Cont’d) 10.4.3.4 Output Compare In this section, the index, i, may because there are two output compare functions in the 16- bit timer. This function can be used to control an output waveform or ...
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ST72325xx 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi pin ...
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TIMER (Cont’d) Figure 52. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 53. Output Compare Timing Diagram, f INTERNAL CPU CLOCK ...
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ST72325xx 16-BIT TIMER (Cont’d) 10.4.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the ...
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TIMER (Cont’d) Figure 54. One Pulse Mode Timing Example IC1R 01F8 COUNTER ICAP1 OCMP1 Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Figure 55. Pulse Width Modulation Mode Timing Example with 2 Output Compare ...
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ST72325xx 16-BIT TIMER (Cont’d) 10.4.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode ...
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TIMER (Cont’d) 10.4.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is ...
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ST72325xx 16-BIT TIMER (Cont’d) 10.4.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the ...
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TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal ...
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ST72325xx 16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read/Write (bits 7:3 read only) Reset Value: xxxx x0xx (xxh) 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD Bit 7 = ICF1 Input Capture Flag input capture (reset value ...
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TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 MSB INPUT ...
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ST72325xx 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 (OC2LR) ...
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TIMER (Cont’d) Table 19. 16-Bit Timer Register Map and Reset Values Address Register 7 (Hex.) Label Timer A: 32 CR1 ICIE Timer B: 42 Reset Value 0 Timer A: 31 CR2 OC1E Timer B: 41 Reset Value 0 Timer ...
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ST72325xx 10.5 SERIAL PERIPHERAL INTERFACE (SPI) 10.5.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) – SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves indi- vidually and to avoid contention on the data lines. Slave SS inputs can be driven ...
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The ...
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 60). Note: The idle state of SCK must correspond to the polarity ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.5 Error Flags 10.5.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and an ...
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.5.4 Single Master Systems A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 62). The master device selects the individual slave de- vices ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ation ...
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when ...
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) Table 21. SPI Register Map and Reset Values Address Register 7 (Hex.) Label SPIDR MSB 0021h Reset Value x SPICR SPIE 0022h Reset Value 0 SPICSR SPIF 0023h Reset Value 0 102/197 ...
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SERIAL COMMUNICATIONS INTERFACE (SCI) 10.6.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range ...
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 63. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU 104/197 Read Received Data Register (RDR) Received ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1. It contains six dedicated reg- isters: – Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A ...
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the ...
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 65. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 CONVENTIONAL BAUD ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. – A break is received. When the ...
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.7 Parity Control Parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the PCE bit in the SCICR1 register. Depending on the frame length ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: – Deviation due to transmitter error (Local TRA oscillator error of the transmitter or the trans- mitter is transmitting at a ...
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/re- ceiving until ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.7 Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content ...
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE TE Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: ...
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The Data register ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR ...
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ST72325xx SERIAL COMMUNICATION INTERFACE (Cont’d) Table 24. SCI Register Map and Reset Values Address Register 7 (Hex.) Label SCISR TDRE 0050h Reset Value 1 SCIDR MSB 0051h Reset Value x SCIBRR SCP1 0052h Reset Value 0 SCICR1 R8 0053h Reset ...
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I C BUS INTERFACE (I2C) 10.7.1 Introduction 2 The I C Bus Interface serves as an interface be- tween the microcontroller and the serial I provides both multimaster and slave functions, 2 and controls all I C bus-specific ...
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ST72325xx BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. 2 The I C interface address and/or general call ad- dress can be selected by software. 2 The speed of the I C interface may ...
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I C BUS INTERFACE (Cont’d) 10.7.4 Functional Description Refer to the CR, SR1 and SR2 registers in 10.7.7. for the bit definitions default the I C interface operates in Slave mode (M/SL bit is cleared) except when ...
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ST72325xx INTERFACE (Cont’d) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. SMBus Compatibility 2 ...
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I C BUS INTERFACE (Cont’d) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the inter- nal shift register. The master waits ...
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ST72325xx BUS INTERFACE (Cont’d) Figure 69. Transfer Sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A Data1 EV1 EV3 7-bit Master receiver: S Address A EV5 EV6 7-bit Master transmitter: S ...
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I C BUS INTERFACE (Cont’d) 10.7.5 Low Power Modes Mode 2 No effect interface. WAIT interrupts cause the device to exit from WAIT mode registers are frozen. 2 HALT In ...
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ST72325xx BUS INTERFACE (Cont’d) 10.7.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h ENGC START ACK Bit 7:6 = Reserved. Forced hardware. ...
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I C BUS INTERFACE (Cont’ STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 7 EVF ADD10 TRA BUSY BTF Bit 7 = EVF Event flag. This bit is set by hardware as soon ...
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ST72325xx BUS INTERFACE (Cont’d) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1 cleared by hardware after detecting a Stop condition on ...
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I C BUS INTERFACE (Cont’ CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 Bit 7 = FM/SM Fast/Standard I This bit is set and cleared by ...
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ST72325xx BUS INTERFACE (Cont’ OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h) 7 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 7-bit Addressing Mode Bit 7:1 = ADD[7:1] Interface address. ...
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I²C BUS INTERFACE (Cont’d) 2 Table 25 Register Map and Reset Values Address Register 7 Label (Hex.) I2CCR 0018h Reset Value 0 I2CSR1 EVF 0019h Reset Value 0 I2CSR2 001Ah Reset Value 0 I2CCCR FM/SM 001Bh Reset Value ...
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ST72325xx 10.8 10-BIT A/D CONVERTER (ADC) 10.8.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels ...
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A/D CONVERTER (ADC) (Cont’d) 10.8.3 Functional Description The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V ) ...
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ST72325xx 10-BIT A/D CONVERTER (ADC) (Cont’d) 10.8.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 CH3 Bit 7 = EOC End of Conversion This bit is set ...
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A/D CONVERTER (Cont’d) Table 26. ADC Register Map and Reset Values Address Register 7 (Hex.) Label ADCCSR EOC 0070h Reset Value 0 ADCDRH D9 0071h Reset Value 0 ADCDRL 0072h Reset Value SPEED ADON 0 ...
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ST72325xx 11 INSTRUCTION SET 11.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
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ST72325xx INSTRUCTION SET OVERVIEW (Cont’d) 11.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch ...
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ST72325xx INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true ...
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INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset ...
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ST72325xx 12 ELECTRICAL CHARACTERISTICS 12.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 12.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions ...
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ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 12.2.1 Voltage Characteristics Symbol ...
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ST72325xx 12.2.3 Thermal Characteristics Symbol T Storage temperature range STG T Maximum junction temperature (see J 12.3 OPERATING CONDITIONS 12.3.1 General Operating Conditions Symbol Parameter f Internal clock frequency CPU Standard voltage range (except Flash Write/Erase Operating Voltage ...
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OPERATING CONDITIONS (Cont’d) 12.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V Symbol Parameter Reset release threshold V IT+(LVD) (V rise) DD Reset generation threshold V IT-(LVD) (V fall LVD voltage threshold ...
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ST72325xx 12.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consump- tion, the two current values ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.2 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consump- tion, ...
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ST72325xx SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.3 On-Chip Peripherals Measured on LQFP64 generic board T Symbol Parameter I 16-bit Timer supply current DD(TIM) I ART PWM supply current DD(ART SPI supply current DD(SPI SCI supply current DD(SCI) ...
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CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 12.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = Δt v(IT v(IT) c(INST) 12.5.2 External Clock Source Symbol Parameter ...
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ST72325xx CLOCK AND TIMING CHARACTERISTICS (Cont’d) 12.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph is based on characterization results with specified typical ...
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Figure 76. Typical Application with a Crystal or Ceramic Resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS The relatively low value of the RF resistor, offers a good protection against issues resulting from use in a humid ...
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ST72325xx CLOCK AND TIMING CHARACTERISTICS (Cont’d) f OSC Supplier (MHz Notes: 1. Resonator characteristics given by the ceramic resonator manufacturer. 2. SMD = [-R0: Plastic tape package ( LEAD = [-A0: Flat pack package (Radial taping ...
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CLOCK CHARACTERISTICS (Cont’d) 12.5.4 RC Oscillators Symbol Parameter Internal RC oscillator frequency f OSC (RCINT) See Figure 77 Figure 77. Typical f OSC(RCINT) 4 3.8 3.6 3.4 3 (°C) A Conditions T =25°C, V =5V ...
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ST72325xx CLOCK CHARACTERISTICS (Cont’d) 12.5.5 Clock Security System (CSS) Symbol Parameter f Safe Oscillator Frequency SFOSC Note: 1. Data based on characterization results. 12.5.6 PLL Characteristics Symbol Parameter f PLL input frequency range OSC Δ Instantaneous PLL ...
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MEMORY CHARACTERISTICS 12.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 12.6.2 FLASH Memory DUAL VOLTAGE HDFLASH MEMORY Symbol Parameter f Operating frequency CPU V Programming voltage Supply current ...
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ST72325xx 12.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 12.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is ...
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EMC CHARACTERISTICS (Cont’d) 12.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the ...
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ST72325xx EMC CHARACTERISTICS (Cont’d) 12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, ...
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I/O PORT PIN CHARACTERISTICS 12.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys Injected Current on PB0 (Flash ...
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ST72325xx I/O PORT PIN CHARACTERISTICS (Cont’d) 12.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 81) 1) ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 84. Typical V vs 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 3.5 4 Vdd(V ) Figure 85. Typical V vs ...
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ST72325xx 12.9 CONTROL PIN CHARACTERISTICS 12.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V Output low level ...
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CONTROL PIN CHARACTERISTICS (Cont’d) Figure 87. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01μF Figure 88. RESET pin protection when LVD is disabled. USER EXTERNAL RESET CIRCUIT 0.01μF Required Note 1: – The reset network protects the ...
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ST72325xx CONTROL PIN CHARACTERISTICS (Cont’d) 12.9.2 ICCSEL/V Pin PP Subject to general operating conditions for V Symbol Parameter I Input leakage current L Figure 89. Two typical Applications with ICCSEL/V ICCSEL/V PP ST72XXX Notes: 1. Data based on design simulation ...
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TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for V Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out- put compare, input capture, external clock, PWM output...). 12.10.1 8-Bit PWM-ART Auto-Reload Timer Symbol ...
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ST72325xx 12.11 COMMUNICATION INTERFACE CHARACTERISTICS 12.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. CPU A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 91. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure 92. SPI Master ...
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ST72325xx COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 2 12.11 Inter IC Control Interface Subject to general operating conditions for V , and T unless otherwise specified CPU Symbol Parameter t SCL clock low time w(SCLL) t SCL ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) The following table gives the values to be written in the I2CCCR register to obtain the required I SCL line frequency. Table 29. SCL Frequency Table f f SCL V = 4.1 V (kHz ...
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ST72325xx 12.12 10-BIT ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Analog reference voltage AREF V Conversion voltage range AIN Positive input leakage current for analog input I lkg Negative input ...
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ADC CHARACTERISTICS (Cont’d) Figure 94. R max AIN ADC (pF) PARASITIC Figure 96. Typical A/D Converter Application R AIN V AIN C Notes ...
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ST72325xx ADC CHARACTERISTICS (Cont’d) 12.12.1 Analog Power Supply and Reference Pins Depending on the MCU pin count, the package may feature separate V AREF power supply pins. These pins supply power to the A/D converter cell and function as the ...
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ADC CHARACTERISTICS (Cont’d) 12.12.3 ADC Accuracy 1) Conditions: V =5V DD Symbol Parameter Total unadjusted error Offset error Gain Error Differential linearity error D 1) ...
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ST72325xx 13 PACKAGE CHARACTERISTICS 13.1 PACKAGE MECHANICAL DATA Figure 99. 64-Pin Low Profile Quad Flat Package (14x14 174/197 A Dim. A2 Min 0.05 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b b 0.30 0.37 0.45 ...
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Figure 100. 64-Pin Low Profile Quad Flat Package (10 x10 Figure 101. 48-Pin Low Profile Quad Flat Package θ ...
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ST72325xx Figure 102. 44-Pin Low Profile Quad Flat Package D D1 176/197 Dim θ Note 1. ...
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PACKAGE MECHANICAL DATA (Cont’d) Figure 103. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width b2 D Figure 104. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width ...
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ST72325xx PACKAGE MECHANICAL DATA (Cont’d) Figure 105. 32-Pin Low Profile Quad Flat Package - D D1 178/197 inches Dim. Min Typ Max Min Typ A 1.60 A1 0.05 ...
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THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T Maximum junction temperature Jmax Notes: 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from ...
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ST72325xx 13.3 SOLDERING INFORMATION In order to meet environmental requirements, ■ ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the ...
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ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH) as well as in factory coded versions (ROM/FASTROM). ST72325 devices are ROM versions. ST72P325 devices are Factory Advanced Service Technique ROM ...
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ST72325xx ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) OPT0= FMP_R Flash memory read-out protection Read-out protection, when selected, provides a protection against Program Memory content ex- traction and against write access to Flash memo- ry. Erasing the option bytes when ...
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... STMicroelectronics using the correctly completed OPTION LIST appended. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide de- tailed information on contractual points. Caution: The Readout Protection binary value is inverted between ROM and FLASH products ...
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ST72325xx Figure 106. Ordering information scheme Example: Family ST7 microcontroller family Memory type F: Flash Blank : ROM P = FASTROM Sub-family 325 No. of pins ...
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... Reference/ROM Code The ROM code name is assigned by STMicroelectronics. ROM code must be sent in .S19 format. .Hex extension cannot be processed. ...
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... Reference/ROM Code The ROM code name is assigned by STMicroelectronics. ROM code must be sent in .S19 format. .Hex extension cannot be processed. ...
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... DEVELOPMENT TOOLS Development tools for the ST7 microcontrollers in- clude a complete range of hardware systems and software tools from STMicroelectronics and third- party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller pe- ripherals, develop and debug your application, and program your microcontrollers. ...
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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) Table 31. Suggested List of Socket Types Device LQFP64 14 x14 LQFP64 10 x10 LQFP48 7 X7 LQFP44 10 X10 LQFP32 14.3.4 Socket and Emulator Information For information on the type ...
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ST7 APPLICATION NOTES Table 32. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY ...
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Table 32. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK ...
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Table 32. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO- AN1179 GRAMMING) AN1446 USING THE ...
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KNOWN LIMITATIONS 15.1 ALL DEVICES 15.1.1 Unexpected Reset Fetch If an interrupt request occurs while a “POP CC” in- struction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the RESET ...
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LD sema,A IRET Case 2: Writing to PxOR or PxDDR with Global In- terrupts Disabled: SIM ; set the interrupt mask LD A,PFDR AND A,#$02 LD X,A ; store the level before writing to PxOR/PxDDR LD A,#$90 LD PFDDR,A; Write ...
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KNOWN LIMITATIONS (Cont’d) 15.1.4 SCI Wrong Break duration Description A single break character is sent by setting and re- setting the SBK bit in the SCICR2 register. In some cases, the break character may have a long- er duration than ...
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KNOWN LIMITATIONS (Cont’d) 15.1.8 Pull-up always active on PE2 The I/O port internal pull-up is always active on I/O port E2 result, if PE2 is in output mode low level, current consumption in Halt/Active Halt mode is increased. ...
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REVISION HISTORY Table 33. Revision History Date Revision 26-Sep-2005 1 Initial release Modified LQFP48 pinout, added S device ordering information Modified Note 4 on Added caution about reset vector in unprogrammed Flash devices in Removed EMC protective circuitry in ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...