DSPIC30F6013-20I/PF Microchip Technology, DSPIC30F6013-20I/PF Datasheet - Page 2
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DSPIC30F6013-20I/PF
Manufacturer Part Number
DSPIC30F6013-20I/PF
Description
IC DSPIC MCU/DSP 132K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6014-20IPF.pdf
(228 pages)
2.DSPIC30F6014-20IPF.pdf
(22 pages)
3.DSPIC30F6014-20IPF.pdf
(28 pages)
Specifications of DSPIC30F6013-20I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
132KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
DSPIC30F601320IPF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6013-20I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6013-20I/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F6011/6012/6013/6014
TABLE 2:
DS80456D-page 2
Operations
Note 1:
EEPROM
Controller
Compare
Interrupt
Memory
Memory
Module
Timers
Output
Flash
Data
CPU
CPU
CPU
CPU
Data
CPU
CPU
ADC
PSV
DCI
DCI
Only those issues indicated in the last column apply to the current silicon revision.
Modification
32-bit Mode
Slave Mode
Instructions
Instruction
Instruction
Nested DO
Instruction
Instruction
MAC class
Idle Mode
Unsigned
Scanning
Channel
Feature
Address
REPEAT
SILICON ISSUE SUMMARY
with +4
Y Data
DAW.b
Speed
Space
Loops
RTSP
Traps
DISI
MAC
—
—
Number
Item
12.
16.
10.
11.
13.
14.
15.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Data EEPROM is operational at 20 MIPS.
The Unsigned Integer mode for the MAC-type DSP instructions
does not function as specified.
Sequential MAC instructions, which prefetch data from Y data
space using +4 address modification, will cause an address
error trap.
The Decimal Adjust instruction, DAW.b, may improperly clear the
Carry bit, C (SR<0>).
In certain instructions, fetching one of the operands from
program memory using Program Space Visibility (PSV) will
corrupt specific bits in the STATUS Register, SR.
When using two DO loops in a nested fashion, terminating the
inner-level DO loop by setting the EDT bit (CORCON<11>) will
produce unexpected results.
When a device Reset occurs while an Run-Time Self-
Programming (RTSP) operation is ongoing, code execution may
lead into an address error trap.
When an instruction that writes to a location in the address
range of Y data memory is immediately followed by a MAC-type
DSP instruction that reads a location also resident in Y data
memory, the operations will not be performed as specified.
When a catastrophic overflow of any of the accumulators causes
an arithmetic (math) error trap, the Overflow Status bits need to
be cleared to exit the trap handler.
When a REPEAT loop is interrupted by two or more interrupts in
a nested fashion, an address error trap may be caused.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
The 32-bit general purpose timers do not function as specified
for prescaler ratios other than 1:1.
The Output Compare module will produce a glitch on the output
when an I/O pin is initially set high, and the module is configured
to drive the pin low at a specified time.
The 12-bit ADC scans one channel less than that specified when
configured to perform channel scanning on MUX A inputs and
alternately converting a fixed MUX B input.
In Slave mode, the DCI module does not function correctly when
data communication is configured to start one serial clock after
the frame synchronization pulse.
The DCI module should not be stopped when the device enters
Idle mode.
Issue Summary
© 2010 Microchip Technology Inc.
Revisions
A3 B1 B2
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