SAA-XC866-4FRA BE Infineon Technologies, SAA-XC866-4FRA BE Datasheet - Page 69
![IC MCU 8BIT FLASH PG-TSSOP-38](/photos/12/23/122305/saa-xc866-4fra_be_sml.jpg)
SAA-XC866-4FRA BE
Manufacturer Part Number
SAA-XC866-4FRA BE
Description
IC MCU 8BIT FLASH PG-TSSOP-38
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet
1.SAA-XC866-2FRA_BE.pdf
(114 pages)
Specifications of SAA-XC866-4FRA BE
Core Processor
XC800
Core Size
8-Bit
Speed
86MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
38-TSSOP
For Use With
MCBXC866 - BOARD EVAL FOR INFINEON XC86X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AX8664FRABEXT
SAA-XC866-4FRABEINTR
SAA-XC866-4FRABEINTR
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3.10
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an SAA-XC866 system reset. Hence, routine service of the WDT
confirms that the system is functioning properly. This ensures that an accidental
malfunction of the SAA-XC866 will be aborted in a user-specified time period. In debug
mode, the WDT is suspended and stops counting. Therefore, there is no need to refresh
the WDT during debugging.
Features:
• 16-bit Watchdog Timer
• Programmable reload value for upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of f
• Time-out detection with NMI generation and reset prewarning activation (after which
The WDT is a 16-bit timer incremented by a count rate of f
16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT
can be preset to a user-programmable value via a watchdog service access in order to
modify the watchdog expire time period. The lower 8 bits are reset on each service
access.
Figure 27
Data Sheet
ENWDT
ENWDT_P
a system reset will be performed)
Figure 27
f
PCLK
Watchdog Timer
Logic
WDT Block Diagram
shows the block diagram of the WDT unit.
1:128
1:2
PCLK
/2 or f
WDTIN
MUX
66
PCLK
/128
WDT Low Byte
Control
WDT
Overflow/Time-out Control &
Window-boundary control
Clear
PCLK
Functional Description
WDT High Byte
WDTWINB
/2 or f
WDTREL
PCLK
SAA-XC866
V1.5, 2010-09
/128. This
WDTTO
WDTRST
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