HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 272
HD64F3664FPV
Manufacturer Part Number
HD64F3664FPV
Description
IC H8/3664 MCU FLASH 32K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of HD64F3664FPV
Core Size
16-Bit
Program Memory Size
32KB (32K x 8)
Oscillator Type
External
Core Processor
H8/300H
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
No. Of I/o's
29
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/300H
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
MURATA
Quantity:
34 000
Company:
Part Number:
HD64F3664FPV
Manufacturer:
HD
Quantity:
465
Company:
Part Number:
HD64F3664FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
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Manufacturer:
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Quantity:
20 000
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Section 15 I
15.3.5
I
interface.
Rev. 6.00 Mar. 24, 2006 Page 242 of 412
REJ09B0142-0600
Bit
7
6
5
4
2
C bus control register (ICCR) consists of the control bits and interrupt request flags of I
I
2
Bit Name
ICE
IEIC
MST
TRS
2
C Bus Control Register (ICCR)
C Bus Interface (IIC)
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
I
When this bit is set to 1, the I
enabled to send/receive data and drive the bus since it
is connected to the SCL and SDA pins. ICMR and
ICDR can be accessed.
When this bit is cleared, the module is halted and
separated from the SCL and SDA pins. SAR and SARX
can be accessed.
I
When this bit is 1, Interrupts are enabled by IRIC.
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode of the I
format. In slave receive mode, the R/W bit in the first
frame immediately after the start automatically sets
these bits in receive mode or transmit mode by using
hardware. The settings can be made again for the bits
that were set/cleared by hardware, by reading these
bits. When the TRS bit is intended to change during a
transfer, the bit will not be switched until the frame
transfer is completed, including acknowledgement.
2
2
C Bus Interface Enable
C Bus Interface Interrupt Enable
2
C bus interface module is
2
C bus
2
C bus
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