R5F21276SNFP#U0 Renesas Electronics America, R5F21276SNFP#U0 Datasheet - Page 235
R5F21276SNFP#U0
Manufacturer Part Number
R5F21276SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Specifications of R5F21276SNFP#U0
Core Size
16/32-Bit
Program Memory Size
32KB (32K x 8)
Core Processor
R8C
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
No. Of I/o's
25
Ram Memory Size
1.5KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
2.2V To 5.5V
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Table 14.22
j = A, B, or C
Count source
Count operation
PWM waveform
Count start conditions
Count stop conditions
Interrupt request
generation timing
TRCIOA/TRCTRG pin
function
TRCIOB pin function
TRCIOC and TRCIOD
pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
Sep 26, 2008
Item
Specifications of PWM2 Mode
Page 216 of 453
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to TRCCLK pin
Increment TRC register
PWM period: 1/fk × (m + 1) (no TRCTRG input)
Active level width: 1/fk × (n - p)
Wait time from count start or trigger: 1/fk × (p + 1)
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b
• 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL
• The count stops due to a compare match with TRCGRA while the CSEL bit in the
• Compare match (contents of TRC and TRCGRj registers match)
• The TRC register overflows
Programmable I/O port or TRCTRG input
PWM output
Programmable I/O port
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt
input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• External trigger and valid edge selected
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff of Pulse
• Digital filter (Refer to 14.3.3.3 Digital Filter.)
disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).
(TRCTRG trigger enabled) and the TSTART bit in the TRCMR register is set to 1
(count starts).
bit in the TRCCR2 register is set to 0 or 1.
TRCCR2 register is set to 1
Output.)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
1 (count starts) is written to the TSTART bit in the TRCMR register.
A trigger is input to the TRCTRG pin
The TRCIOB pin outputs the initial level in accordance with the value of the TOB
bit in the TRCCR1 register. The TRC register retains the value before count stops.
The TRCIOB pin outputs the initial level. The TRC register retains the value before
count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is
set to 0000h if the CCLR bit in the TRCCR1 register is set to 1.
The edge or edges of the signal input to the TRCTRG pin can be used as the
PWM output trigger: rising edge, falling edge, or both rising and falling edges
TRCIOB output
TRCTRG input
m+1
n+1
p+1
n-p
Specification
(TRCTRG: Rising edge, active level is “H”)
n+1
p+1
n-p
14. Timers
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