PXAS37KBA,512 NXP Semiconductors, PXAS37KBA,512 Datasheet - Page 32

• Manufacturer Part Number: PXAS37KBA,512
• Description: IC XA MCU 16BIT 32K OTP 68-PLCC
• Manufacturer: NXP Semiconductors
• Series: XAr

Specifications of PXAS37KBA,512

• Core Processor: XA
• Core Size: 16-Bit
• Speed: 30MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Processor Series: PXAS3x
• Core: 80C51
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-3536-5; 935262377512; PXAS37KBA

Philips Semiconductors
INTERRUPTS
XA-S3 interrupt sources include the following:
There are a total of 17 hardware interrupt sources, enable bits,
priority bit sets, etc.
The XA-S3 supports a total of 17 maskable event interrupt sources
(for the various XA peripherals), seven software interrupts, 5
EXCEPTION/TRAPS PRECEDENCE
2000 Dec 01
Reset (h/w, watchdog, s/w)
Breakpoint
Trace
Stack Overflow
Divide by 0
User RETI
TRAP 0–15 (software)
External interrupts 0 and 1 (2)
Timer 0, 1, and 2 interrupts (3)
PCA: 1 global and 5 channel interrupts (6)
A/D interrupt (1)
UART 0 transmitter and receiver interrupts (2)
UART 1 transmitter and receiver interrupts (2)
I
Software interrupts (7)
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
RSTSRC
Not bit Addressable
Reset Value: see below
2
2
C interrupt (1)
C, 2 UARTs, 16 MB address range
BIT
RSTSRC.7
RSTSRC.6
RSTSRC.5
RSTSRC.4
RSTSRC.3
RSTSRC.2
RSTSRC.1
RSTSRC.0
DESCRIPTION
Address:463h
SYMBOL
—
—
—
—
—
R_WD
R_CMD
R_EXT
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Reserved for future use. Should not be set to 1 by user programs.
Indicates that the last reset was caused by a watchdog timer overflow.
Indicates that the last reset was caused by execution of the RESET instruction.
Indicates that the last reset was caused by the external RST input.
MSB
—
Figure 24. Reset source register (RSTSRC)
—
VECTOR ADDRESS
—
000C–000F
0008–000B
0000–0003
0004–0007
0010–0013
0014–0017
0040–007F
32
—
exception interrupts (plus reset), and 16 traps. The maskable event
interrupts share a global interrupt disable bit (the EA bit in the IEL
register) and each also has a separate individual interrupt enable bit
(in the IEL or IEH registers). Only three bits of the IPA register
values are used on the XA-S3. Each event interrupt can be set to
occur at one of 8 priority levels via bits in the Interrupt Priority (IP)
registers, IPA0 through IPA5. The value 0 in the IPA field gives the
interrupt priority 0, in effect disabling the interrupt. A value of 1 gives
the interrupt a priority of 9, the value 2 gives priority 10, etc. The
result is the same as if all four bits were used and the top bit set for
all values except 0. Details of the priority scheme may be found in
the XA User Guide .
The complete interrupt vector list for the XA-S3, including all
4 interrupt types, is shown in the following tables. The tables include
the address of the vector for each interrupt, the related priority
register bits (if any), and the arbitration ranking for that interrupt
source. The arbitration ranking determines the order in which
interrupts are processed if more than one interrupt of the same
priority occurs simultaneously.
—
R_WD R_CMD R_EXT
ARBITRATION RANKING
SU00942
LSB
0 (High)
1
1
1
1
1
1
Preliminary specification
XA-S3