PXAS37KBBE,557 NXP Semiconductors, PXAS37KBBE,557 Datasheet - Page 18

• Manufacturer Part Number: PXAS37KBBE,557
• Description: IC XA MCU 16BIT 32K OTP 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: XAr

Specifications of PXAS37KBBE,557

• Core Processor: XA
• Core Size: 16-Bit
• Speed: 30MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-LQFP
• Processor Series: PXAS3x
• Core: 80C51
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-3537; 935262379557; PXAS37KBBE

Philips Semiconductors
I
The I
I
rate selection. The I
specification, but may be used at rates up to 400 kHz
(non-conforming).
Important: Before the I
P5.6 and 5.7, which correspond to the I
respectively, must be set to the open drain mode.
The processor interfaces to the I
special function registers: I2CON (I
status register), I2DAT (I
address register). The I
bus via two port 5 pins: P5.6/SCL (serial clock line) and P5.7/SDA
(serial data line).
The Control Register, I2CON
This register is shown in Figure 6. Two bits are affected by the I
hardware: the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present on the I
bus. The STO bit is also cleared when ENA = “0”.
ENA, the I
ENA = 0: When ENA is “0”, the SDA and SCL outputs are not
driven. SDA and SCL input signals are ignored, SIO1 is in the “not
addressed” slave state, and the STO bit in I2CON is forced to “0”.
No other bits are affected. P5.6 and P5.7 may be used as open
drain I/O ports.
ENA = 1: When ENA is “1”, SIO1 is enabled. The P5.6 and P5.7
port latches must be set to logic 1.
ENA should not be used to temporarily release the I
when ENA is reset, the I
used instead (see description of the AA flag in the following text).
In the following text, it is assumed the ENA = “1”.
STA, the START flag
STA = 1: When the STA bit is set to enter a master mode, the I
hardware checks the status of the I
condition if the bus is free. If the bus is not free, the I
waits for a STOP condition (which will free the bus) and generates a
START condition after a delay of a half clock period of the internal
serial clock generator.
If STA is set while the I
one or more bytes are transmitted or received, the hardware
transmits a repeated START condition. STA may be set at any time.
STA may also be set when the I
STA = 0: When the STA bit is reset, no START condition or
repeated START condition will be generated.
STO, the STOP flag
STO = 1: When the STO bit is set while the I
master mode, a STOP condition is transmitted to the I
the STOP condition is detected on the bus, the hardware clears the
STO flag. In a slave mode, the STO flag may be set to recover from
an error condition. In this case, no STOP condition is transmitted to
the I
has been received and switches to the defined “not addressed” slave
receiver mode. The STO flag is automatically cleared by hardware.
2000 Dec 01
2
2
C interface found on devices such as the 8xC552 except for the
C Interface
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
2
2
C, 2 UARTs, 16 MB address range
2
C bus. However, the hardware behaves as if a STOP condition
C interface on the XA-S3 is identical to the standard byte-style
2
C Enable Bit
2
C interface conforms to the 100 kHz I
2
2
C interface is already in a master mode and
C control logic interfaces to the external I
2
2
2
C-bus status is lost. The AA flag should be
C data register), and I2ADR (I
C interface may be used, the port pins
2
2
C interface is an addressed slave.
C logic via the following four
2
2
C control register), I2STA (I
C bus and generates a START
2
C functions SCL and SDA
2
C interface is in a
2
2
2
C-bus since,
C interface
C bus. When
2
C slave
2
C
2
2
C
2
C
2
C
2
C
C
18
If the STA and STO bits are both set, then a STOP condition is
transmitted to the I
slave mode, the hardware generates an internal STOP condition
which is not transmitted). The I
condition.
STO = 0: When the STO bit is reset, no STOP condition will be
generated.
SI, the Serial Interrupt flag
SI = 1: When the SI flag is set, and the EA (interrupt system
enable) and EI2 (I
interrupt is requested. SI is set by hardware when one of 25 of the
26 possible I
not cause SI to be set is state F8H, which indicates that no relevant
state information is available.
While SI is set, the low period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A high level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
SI = 0: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line.
AA, the Assert Acknowledge flag
AA = 1: If the AA flag is set, an acknowledge (low level to SDA) will
be returned during the acknowledge clock pulse on the SCL line when:
AA = 0: If the AA flag is reset, a not acknowledge (high level to
SDA) will be returned during the acknowledge clock pulse on the
SCL line when:
When the I
state C8H will be entered after the last serial data byte is
transmitted. When SI is cleared, the I
enters the not addressed slave receiver mode, and the SDA line
remains at a high level. In state C8H, the AA flag can be set again
for future address recognition.
When the I
slave address and the general call address are ignored. Consequently,
no acknowledge is returned, and a serial interrupt is not requested.
Thus, the hardware can be temporarily released from the I
while the bus status is monitored. While the hardware is released from
the bus, START and STOP conditions are detected, and serial data is
shifted in. Address recognition can be resumed at any time by setting
the AA flag. If the AA flag is set when the part’s own slave address or
the general call address has been partly received, the address will be
recognized at the end of the byte transmission.
The “own slave address” has been received.
The general call address has been received while the general call
bit (GC) in I2ADR is set.
A data byte has been received while the I
master receiver mode.
A data byte has been received while the I
addressed slave receiver mode.
A data byte has been received while the I
master receiver mode.
A data byte has been received while the I
addressed slave receiver mode.
2
2
C interface is in the not addressed slave mode, its own
C interface is in the addressed slave transmitter mode,
2
C interface states is entered. The only state that does
2
2
C interrupt enable) bits are also set, an I
C bus if the interface is in a master mode (in a
2
C interface then transmits a START
2
C interface leaves state C8H,
2
2
2
2
Preliminary specification
C interface is in the
C interface is in the
C interface is in the
C interface is in the
XA-S3
2
C bus
2
C