ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet - Page 25

IC AVR MCU 128K 16MHZ 5V 64TQFP

ATMEGA128-16AU

Manufacturer Part Number
ATMEGA128-16AU
Description
IC AVR MCU 128K 16MHZ 5V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128-16AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4096Byte
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Rev. 2467C-02/02
2467VS–AVR–02/11
12. Added Calibrated RC Oscillator characterization curves in section
13. Updated
14. Added a note regarding usage of Timer/Counter0 combined with the clock. See
1. Corrected Description of Alternate Functions of Port G
2. Added JTAG Version Numbers for rev. F and rev. G
3
4. Corrected
5. Added some Characterization Data in Section
6. Removed Alternative Algortihm for Leaving JTAG Programming Mode.
7. Added Description on How to Access the Extended Fuse Byte Through JTAG Pro-
teristics” on page
More details regarding use of the TWI Power-down operation and using the TWI as master
with low TWBRR values are added into the data sheet. Added the note at the end of the
Rate Generator Unit” on page
on page
“XTAL Divide Control Register – XDIV” on page
Corrected description of TOSC1 and TOSC2 in
Updated Table 100 on page 256.
Added Some Preliminary Test Limits and Characterization Data
Removed some of the TBD's in the following tables and pages:
Table 19 on page
page
See “Leaving Programming Mode” on page 315.
gramming Mode.
See
317.
“Programming the Fuses” on page 317
320,
204.
“Two-wire Serial Interface”
Table 134 on page
“Ordering Information” on page
50,
333.
Table 20 on page
203. Added the description at the end of
323, and Table 136 on page 328.
section.
54,
“DC Characteristics” on page
and
15.
“Alternate Functions of Port G” on page
“Reading the Fuses and Lock Bits” on page
“Typical Characteristics” on page
36.
ATmega128
“Address Match Unit”
“Typical Charac-
318,
Table 131 on
333..
84.
“Bit
25

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