PIC18LF452-I/PT Microchip Technology, PIC18LF452-I/PT Datasheet - Page 157
![IC MCU FLASH 16KX16 A/D 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF452-I/PT
Manufacturer Part Number
PIC18LF452-I/PT
Description
IC MCU FLASH 16KX16 A/D 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
8.PIC18F452-EP.pdf
(332 pages)
Specifications of PIC18LF452-I/PT
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
MSSP/SPI/I2C/PSP/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Data Rom Size
256 B
Height
1 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF452-I/PT
Manufacturer:
XILINX
Quantity:
349
Company:
Part Number:
PIC18LF452-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF452-I/PT
Manufacturer:
MICROCH
Quantity:
20 000
15.4.10
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the buffer full flag bit, BF, and allow the baud rate
generator to begin counting and start the next transmis-
sion. Each bit of address/data will be shifted out onto
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification parameter 106). SCL
is held low for one baud rate generator rollover count
(T
high (see data setup time specification parameter 107).
When the SCL pin is released high, it is held that way
for T
for that duration and some hold time after the next fall-
ing edge of SCL. After the eighth bit is shifted out (the
falling edge of the eighth clock), the BF flag is cleared
and the master releases SDA. This allows the slave
device being addressed to respond with an ACK bit
during the ninth bit time if an address match occurred
or if data was received properly. The status of ACK is
written into the ACKDT bit on the falling edge of the
ninth clock. If the master receives an Acknowledge, the
Acknowledge status bit, ACKSTAT, is cleared. If not,
the bit is set. After the ninth clock, the SSPIF bit is set
and the master clock (baud rate generator) is sus-
pended until the next data byte is loaded into the
SSPBUF, leaving SCL low and SDA unchanged
(Figure 15-21).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
15.4.10.1
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
15.4.10.2
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
© 2006 Microchip Technology Inc.
BRG
BRG
). Data should be valid before SCL is released
. The data on the SDA pin must remain stable
I
TRANSMISSION
2
C MASTER MODE
BF Status Flag
WCOL Status Flag
15.4.10.3
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge (ACK
= 0), and is set when the slave does not Acknowledge
(ACK = 1). A slave sends an Acknowledge when it has
recognized its address (including a general call) or
when the slave has properly received its data.
15.4.11
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the baud rate genera-
tor is suspended from counting, holding SCL low. The
MSSP is now in IDLE state, awaiting the next com-
mand. When the buffer is read by the CPU, the BF flag
bit is automatically cleared. The user can then send an
Acknowledge bit at the end of reception, by setting the
Acknowledge
(SSPCON2<4>).
15.4.11.1
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
15.4.11.2
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
15.4.11.3
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note:
In the MSSP module, the RCEN bit must
be set after the ACK sequence or the
RCEN bit will be disregarded.
I
2
ACKSTAT Status Flag
C MASTER MODE RECEPTION
BF Status Flag
SSPOV Status Flag
WCOL Status Flag
sequence
PIC18FXX2
enable
DS39564C-page 155
bit,
ACKEN