AT89C51CC03U-RDRIM Atmel, AT89C51CC03U-RDRIM Datasheet - Page 68

IC 8051 MCU FLASH 64K 64VQFP

AT89C51CC03U-RDRIM

Manufacturer Part Number
AT89C51CC03U-RDRIM
Description
IC 8051 MCU FLASH 64K 64VQFP
Manufacturer
Atmel
Series
AT89C CANr

Specifications of AT89C51CC03U-RDRIM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03URDRTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51CC03U-RDRIM
Manufacturer:
Atmel
Quantity:
10 000
Timers/Counters
Timer/Counter
Operations
Timer 0
68
AT89C51CC03
The AT89C51CC03 implements two general-purpose, 16-bit Timers/Counters. Such are
identified as Timer 0 and Timer 1, and can be independently configured to operate in a
variety of modes as a Timer or an event Counter. When operating as a Timer, the
Timer/Counter runs for a programmed length of time, then issues an interrupt request.
When operating as a Counter, the Timer/Counter counts negative transitions on an
external pin. After a preset number of counts, the Counter issues an interrupt request.
The various operating modes of each Timer/Counter are described in the following
sections.
A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to
form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 30)
turns the Timer on by allowing the selected input to increment TLx. When TLx overflows
it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON
register. Setting the TRx does not clear the THx and TLx Timer registers. Timer regis-
ters can be accessed to obtain the current count or to enter preset values. They can be
read at any time but TRx bit must be cleared to preset their values, otherwise the behav-
ior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer operation or Counter operation by selecting the
divided-down peripheral clock or external pin Tx as the source for the counted signal.
TRx bit must be cleared when changing the mode of operation, otherwise the behavior
of the Timer/Counter is unpredictable.
For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral
clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock
periods). The Timer clock rate is F
mode.
For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on
the Tx external input pin. The external input is sampled every peripheral cycles. When
the sample is high in one cycle and low in the next one, the Counter is incremented.
Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,
the maximum count rate is F
mode. There are no restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes, it should be held for
at least one full peripheral cycle.
Timer 0 functions as either a Timer or event Counter in four modes of operation.
Figure 35 to Figure 38 show the logical configuration of each mode.
Timer 0 is controlled by the four lower bits of TMOD register (see Figure 31) and bits 0,
1, 4 and 5 of TCON register (see Figure 30). TMOD register selects the method of Timer
gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and
M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control
bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).
For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by
the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer
operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter-
rupt request.
It is important to stop Timer/Counter before changing mode.
PER
/12, i.e. F
PER
/6, i.e. F
OSC
OSC
/24 in standard mode or F
/12 in standard mode or F
4182O–CAN–09/08
OSC
OSC
/12 in X2
/6 in X2

Related parts for AT89C51CC03U-RDRIM