AT89C51CC03U-RDRIM Atmel, AT89C51CC03U-RDRIM Datasheet - Page 47

IC 8051 MCU FLASH 64K 64VQFP

AT89C51CC03U-RDRIM

Manufacturer Part Number
AT89C51CC03U-RDRIM
Description
IC 8051 MCU FLASH 64K 64VQFP
Manufacturer
Atmel
Series
AT89C CANr

Specifications of AT89C51CC03U-RDRIM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03URDRTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51CC03U-RDRIM
Manufacturer:
Atmel
Quantity:
10 000
FSTA Register
Mapping of the Memory Space By default, the user space is accessed by MOVC A, @DPTR instruction for read only.
Launching Programming
4182O–CAN–09/08
Table 14. FSTA Register
FSTA Register (S:D3h)
Flash Status Register
Reset Value= 0000 0000b
The column latches space is made accessible by setting the FPS bit in FCON register.
Writing is possible from 0000h to FFFFh, address bits 6 to 0 are used to select an
address within a page while bits 15 to 7 are used to select the programming address of
the page.
Setting FPS bit takes precedence on the EXTRAM bit in AUXR register.
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-
dance with Table 15. A MOVC instruction is then used for reading these spaces.
Table 15. FM0 Blocks Select Bits
Notes:
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5xh followed by Axh. Table 16 summarizes the memory
spaces to program according to FMOD1:0 bits.
Number
Bit
7-2
7
1
0
FMOD1
1. The column latches reset is a new option introduced in the AT89C51CC03, and is not
0
0
1
1
available in T89C51CC01/2
Mnemonic Description
SEQERR
FLOAD
Bit
6
unusesd
Flash activation sequence error
Set by hardware when the flash activation sequence(MOV FCON 5X and MOV
FCON AX )is not correct (See Error Repport Section)
Clear by software or clear by hardware if the last activation sequence was
correct (previous error are canceled)
Flash Colums latch loaded
Set by hardware when the first data is loaded in the column latches.
Clear by hardware when the activation sequence suceed (flash write sucess, or
reset column latch success)
FMOD0
5
0
1
0
1
FM0 Adressable space
User (0000h-FFFFh)
Extra Row(FF80h-FFFFh)
Hardware Security Byte (0000h)
Column latches reset (note1)
4
3
AT89C51CC03
2
SEQERR
1
FLOAD
0
47

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