ATMEGA3250PV-10AU Atmel, ATMEGA3250PV-10AU Datasheet - Page 62
ATMEGA3250PV-10AU
Manufacturer Part Number
ATMEGA3250PV-10AU
Description
IC MCU AVR 32K FLASH 100-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA3250P-20AU.pdf
(364 pages)
Specifications of ATMEGA3250PV-10AU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, UART, USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Data Rom Size
1 KB
Operating Supply Voltage
1.8 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
A/d Bit Size
10 bit
A/d Channels Available
8
Height
1 mm
Length
14 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
14 mm
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA3250PV-8AU
ATMEGA3250PV-8AU
ATMEGA3250PV-8AU
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12.3.4
12.3.5
12.3.6
12.3.7
8023F–AVR–07/09
PCMSK3 – Pin Change Mask Register 3
PCMSK2 – Pin Change Mask Register 2
PCMSK1 – Pin Change Mask Register 1
PCMSK0 – Pin Change Mask Register 0
• Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30:24
Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT30:24 is set and the PCIE3 bit in EIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT30:24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16
Each PCINT23:16 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23:16 is set and the PCIE2 bit in EIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Note:
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
• Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the cor-
responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Bit
(0x6D)
Read/Write
Initial
Value
Bit
(0x73)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
Bit
(0x6B)
Read/Write
Initial Value
1. PCMSK3 and PCMSK2 are only present in ATmega3250P.
PCINT23
7
PCINT7
R/W
0
PCINT15
R/W
R/W
7
0
R
7
0
7
–
0
PCINT22
6
PCINT6
R/W
0
PCINT30
PCINT14
R/W
R/W
R/W
6
0
6
0
6
0
(1)
(1)
PCINT21
5
PCINT5
R/W
0
PCINT13
PCINT29
R/W
R/W
R/W
5
0
5
0
5
0
PCINT20
4
PCINT4
R/W
0
PCINT12
PCINT28
R/W
R/W
R/W
4
0
4
0
4
0
PCINT19
3
PCINT3
R/W
0
PCINT11
PCINT27
R/W
R/W
R/W
3
0
3
0
3
0
ATmega325P/3250P
2
PCINT2
R/W
0
PCINT18
PCINT10
PCINT26
R/W
R/W
R/W
2
0
2
0
2
0
1
PCINT1
R/W
0
PCINT17
PCINT25
PCINT9
R/W
R/W
R/W
1
0
1
0
1
0
PCINT0
0
R/W
0
PCINT16
PCINT24
PCINT8
R/W
R/W
R/W
0
0
0
0
0
0
PCMSK0
PCMSK2
PCMSK1
PCMSK3
62
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