PIC18F2550-I/SP Microchip Technology, PIC18F2550-I/SP Datasheet - Page 193
PIC18F2550-I/SP
Manufacturer Part Number
PIC18F2550-I/SP
Description
IC PIC MCU FLASH 16KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
7.PIC18F4550-IP.pdf
(430 pages)
8.PIC18LF2455-ISO.pdf
(430 pages)
Specifications of PIC18F2550-I/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2550-I/SP
Manufacturer:
MICROCHIP
Quantity:
2 100
- PIC16F616T-ISL PDF datasheet
- PCM18XR1 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2455-ISO PDF datasheet #4
- PIC18F2455-ISO PDF datasheet #5
- PIC18F2455-ISO PDF datasheet #6
- PIC18F4550-IP PDF datasheet #7
- PIC18LF2455-ISO PDF datasheet #8
- Current page: 193 of 438
- Download datasheet (7Mb)
18.0
PIC18F4455/4550 USB devices provide a Streaming
Parallel Port as a high-speed interface for moving data
to and from an external system. This parallel port
operates as a master port, complete with chip select
and clock outputs to control the movement of data to
slave devices. Data can be channelled either directly to
the USB SIE or to the microprocessor core. Figure 18-1
shows a block view of the SPP data path.
FIGURE 18-1:
REGISTER 18-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1
bit 0
Note:
USB
SIE
CPU
U-0
—
STREAMING PARALLEL PORT
The Streaming Parallel Port is only
available on 40/44-pin devices.
Unimplemented: Read as ‘0’
SPPOWN: SPP Ownership bit
1 = USB peripheral controls the SPP
0 = Microcontroller directly controls the SPP
SPPEN: SPP Enable bit
1 = SPP is enabled
0 = SPP is disabled
PIC18F4455/4550
U-0
—
SPP DATA PATH
SPPCON: SPP CONTROL REGISTER
Logic
SPP
W = Writable bit
‘1’ = Bit is set
U-0
—
CK1SPP
CK2SPP
OESPP
CSSPP
SPP<7:0>
PIC18F2455/2550/4455/4550
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
In addition, the SPP can provide time multiplexed
addressing information along with the data by using the
second strobe output. Thus, the USB endpoint number
can be written in conjunction with the data for that
endpoint.
18.1
The operation of the SPP is controlled by two registers:
SPPCON and SPPCFG. The SPPCON register
(Register 18-1) controls the overall operation of the
parallel port and determines if it operates under USB or
microcontroller
(Register 18-2) controls timing configuration and pin
outputs.
18.1.1
To enable the SPP, set the SPPEN bit (SPPCON<0>).
In addition, the TRIS bits for the corresponding SPP
pins must be properly configured. At a minimum:
• Bits TRISD<7:0> must be set (= 1)
• Bits TRISE<2:1> must be cleared (= 0)
If CK1SPP is to be used:
• Bit TRISE<0> must be cleared (= 0)
If CSPP is to be used:
• Bit TRISB<4> must be cleared (= 0)
U-0
—
SPP Configuration
ENABLING THE SPP
U-0
—
control.
x = Bit is unknown
SPPOWN
The
R/W-0
SPPCFG
DS39632E-page 191
SPPEN
R/W-0
register
bit 0
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