PIC18F4450-I/PT Microchip Technology, PIC18F4450-I/PT Datasheet - Page 163
PIC18F4450-I/PT
Manufacturer Part Number
PIC18F4450-I/PT
Description
IC PIC MCU FLASH 8KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2450-ISO.pdf
(324 pages)
3.PIC18F2450-ISO.pdf
(6 pages)
4.PIC18F2450-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(4 pages)
6.PIC18F2450-ISO.pdf
(4 pages)
7.PIC18F4450-IP.pdf
(322 pages)
Specifications of PIC18F4450-I/PT
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
34
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM163025, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Height
1 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163025 - PIC DEM FULL SPEED USB DEMO BRD444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4450-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2450-ISO PDF datasheet #2
- PIC18F2450-ISO PDF datasheet #3
- PIC18F2450-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- PIC18F2450-ISO PDF datasheet #6
- PIC18F4450-IP PDF datasheet #7
- Current page: 163 of 324
- Download datasheet (6Mb)
15.1.3
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 15-1) begins whenever a Start bit is received and
the ABDEN bit is set. The calculation is self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detection must receive a byte with the value 55h
(ASCII “U”, which is also the LIN bus Sync character)
in order to calculate the proper bit rate. The measure-
ment is taken over both a low and a high bit time in
order to minimize any effects caused by asymmetry of
the incoming signal. After a Start bit, the SPBRG begins
counting up, using the preselected clock source on the
first rising edge of RX. After eight bits on the RX pin, or
the fifth rising edge, an accumulated value totalling the
proper BRG period is left in the SPBRGH:SPBRG
register pair. Once the 5th edge is seen (this should
correspond to the Stop bit), the ABDEN bit is
automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG roll-
overs and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 15-2).
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 15-4 for counter
clock rates to the BRG.
© 2008 Microchip Technology Inc.
AUTO-BAUD RATE DETECT
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. The contents of RCREG should be discarded.
TABLE 15-4:
15.1.3.1
Since the BRG clock is reversed during ABD
acquisition, the EUSART transmitter cannot be used
during ABD. This means that whenever the ABDEN bit
is set, TXREG cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
BRG16
Note:
Note 1: If the WUE bit is set with the ABDEN bit,
0
0
1
1
2: It is up to the user to determine that the
PIC18F2450/4450
BRGH
During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of the BRG16 setting.
Auto-Baud Rate Detection will occur on
the byte following the Break character.
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator fre-
quency and EUSART baud rates are not
possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when
Detection feature.
ABD and EUSART Transmission
0
1
0
1
BRG COUNTER
CLOCK RATES
using
BRG Counter Clock
the
F
F
F
F
OSC
OSC
OSC
OSC
Auto-Baud
DS39760D-page 161
/512
/128
/128
/32
Rate
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