PIC18LF24J50-I/SP Microchip Technology, PIC18LF24J50-I/SP Datasheet - Page 127
PIC18LF24J50-I/SP
Manufacturer Part Number
PIC18LF24J50-I/SP
Description
IC PIC MCU FLASH 16K 2V 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF24J50-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART/I2C/SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, MA180024, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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- Download datasheet (9Mb)
REGISTER 9-1:
REGISTER 9-2:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-2
bit 1
bit 0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
ECCP2OD: ECCP2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
ECCP1OD: ECCP1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
Unimplemented: Read as ‘0’
U2OD: USART2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
U1OD: USART1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
U-0
U-0
—
—
ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1 (BANKED F42h)
ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h)
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F46J50 FAMILY
U-0
U-0
—
—
U-0
U-0
—
—
x = Bit is unknown
x = Bit is unknown
ECCP2OD
R/W-0
R/W-0
U2OD
DS39931C-page 127
ECCP1OD
R/W-0
R/W-0
U1OD
bit 0
bit 0
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