PIC16F722-I/ML Microchip Technology, PIC16F722-I/ML Datasheet - Page 173
![IC PIC MCU FLASH 2KX14 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F722-I/ML
Manufacturer Part Number
PIC16F722-I/ML
Description
IC PIC MCU FLASH 2KX14 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.AC164112.pdf
(302 pages)
2.PIC16F722-ISS.pdf
(8 pages)
3.PIC16F722-ISS.pdf
(10 pages)
4.PIC16F722-ISS.pdf
(32 pages)
5.PIC16F722-ISS.pdf
(2 pages)
6.PIC16F722-ISS.pdf
(8 pages)
Specifications of PIC16F722-I/ML
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
25
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- AC164112 PDF datasheet
- PIC16F722-ISS PDF datasheet #2
- PIC16F722-ISS PDF datasheet #3
- PIC16F722-ISS PDF datasheet #4
- PIC16F722-ISS PDF datasheet #5
- PIC16F722-ISS PDF datasheet #6
- Current page: 173 of 302
- Download datasheet (5Mb)
17.1.2.4
The SS pin allows Synchronous Slave mode operation.
The SPI must be in Slave mode with SS pin control
enabled (SSPM<3:0> = 0100). The associated TRIS bit
for the SS pin must be set, making SS an input.
In Slave Select mode, when:
• SS = 0, The device operates as specified in
• SS = 1, The SPI module is held in Reset and the
FIGURE 17-6:
© 2009 Microchip Technology Inc.
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Section 17.1.2 “Slave Mode”.
SDO pin will be tri-stated.
Note 1: When the SPI is in Slave mode with SS pin
2: If the SPI is used in Slave mode with CKE
control enabled (SSPM<3:0> = 0100), the
SPI module will reset if the SS pin is driven
high.
set, the SS pin control must be enabled.
Slave Select Operation
SLAVE SELECT SYNCHRONIZATION WAVEFORM
bit 7
bit 7
bit 6
PIC16F72X/PIC16LF72X
When the SPI module resets, the bit counter is cleared
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit. Figure 17-6
shows the timing waveform for such a synchronization
event.
17.1.2.5
While in Sleep mode, the slave can transmit/receive
data. The SPI Transmit/Receive Shift register operates
asynchronously to the device on the externally supplied
clock source. This allows the device to be placed in
Sleep mode and data to be shifted into the SPI Trans-
mit/Receive Shift register. When all 8 bits have been
received, the SSP Interrupt Flag bit will be set and if
enabled, will wake the device from Sleep.
Note:
SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.
SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.
Sleep in Slave Mode
bit 7
bit 7
DS41341E-page 173
bit 0
bit 0
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