MM74HC123A Fairchild, MM74HC123A Datasheet

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MM74HC123A

Manufacturer Part Number
MM74HC123A
Description
Dual Retriggerable Monostable Multivibrator
Manufacturer
Fairchild
Datasheet

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© 1999 Fairchild Semiconductor Corporation
MM74HC123AM
MM74HC123ASJ
MM74HC123AMTC
MM74HC123AN
MM74HC123A
Dual Retriggerable Monostable Multivibrator
General Description
The MM74HC123A high speed monostable multivibrators
(one shots) utilize advanced silicon-gate CMOS technol-
ogy. They feature speeds comparable to low power Schot-
tky TTL circuitry while retaining the low power and high
noise immunity characteristic of CMOS circuits.
Each multivibrator features both a negative, A, and a posi-
tive, B, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken low resets the one shot. The MM74HC123A
can be triggered on the positive transition of the clear while
A is held LOW and B is held HIGH.
The MM74HC123A is retriggerable. That is it may be trig-
gered repeatedly while their outputs are generating a pulse
and the pulse will be extended.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques. The out-
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Pin Assignment for DIP, SOIC, SOP and TSSOP
Package Number
Top View
MTC16
M16A
M16D
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS005206.prf
put pulse equation is simply: PW
PW is in seconds, R is in ohms, and C is in farads. All
inputs are protected from damage due to static discharge
by diodes to V
Features
Note: Pin 6 and Pin 14 must be hard-wired to GND.
Typical propagation delay: 25 ns
Wide power supply range: 2V–6V
Low quiescent current: 80 A maximum (74HC Series)
Low input current: 1 A maximum
Fanout of 10 LS-TTL loads
Simple pulse width formula T
Wide pulse range: 400 ns to
Part to part variation: 5% (typ)
Schmitt Trigger A & B inputs enable infinite signal input
rise and fall times.
Package Description
CC
and ground.
Timing Component
September 1983
Revised February 1999
(typ)
RC
(R
EXT
www.fairchildsemi.com
) (C
EXT
); where

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MM74HC123A Summary of contents

Page 1

... The MM74HC123A can be triggered on the positive transition of the clear while A is held LOW and B is held HIGH. The MM74HC123A is retriggerable. That is it may be trig- gered repeatedly while their outputs are generating a pulse and the pulse will be extended. ...

Page 2

... Truth Table Inputs Clear HIGH Level L LOW Level Transition from LOW-to-HIGH Transition from HIGH-to-LOW One HIGH Level Pulse One LOW Level Pulse X Irrelevant Logic Diagram www.fairchildsemi.com Outputs ...

Page 3

... The worst-case leakage current Min Max Units 1000 ns 500 ns 400 125 C A Units 1.5 1.5 V 3.15 3.15 V 4.2 4.2 V 0.3 0.3 V 0.9 0.9 V 1.2 1.2 V 1.9 1.9 V 4.4 4.4 V 5.9 5 3.84 3.7 V 5.34 5.2 V 0.1 0.1 V 0.1 0.1 V 0.1 0 0.33 0.4 V 0.33 0.4 V 5.0 5.0 A 1.0 1 160 A 110 130 A 1.3 1.6 mA 2.6 3.2 mA www.fairchildsemi.com ...

Page 4

... Capacitance (Pins 7 & 15) C Maximum Input IN Capacitance (other inputs) C Power Dissipation (Note 5) PD Capacitance Note 5: C determines the no load dynamic power consumption www.fairchildsemi.com Conditions EXT EXT C 1000 pF EXT EXT Typ 2.0V 77 169 4 ...

Page 5

... Both comparators are “off” with the total device current due only to reverse junction leakages. An added feature of the MM74HC123A is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger independent of FIGURE 1 ...

Page 6

... Typical Distribution of Output Pulse Width, Part to Part Note: R and C are not subjected to temperature. The C is polypropylene. www.fairchildsemi.com clear input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low- ...

Page 7

... Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16A Package Number M16D 7 www.fairchildsemi.com ...

Page 8

... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC16 8 ...

Page 9

... Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. Package Number N16E 2 ...

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