IDT72V295 Integrated Device Technology, IDT72V295 Datasheet

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... Available in the 64-pin Thin Quad Flat Pack (TQFP) • High-performance submicron CMOS technology DESCRIPTION: The IDT72V295/72V2105 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, includ- ing the following: • ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 x 18 DESCRIPTION (CONTINUED) thus longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. • The period required by the retransmit operation is now fixed and short. • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short ...

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... Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V295/72V2105 are fabricated using IDT’s high speed submi- cron CMOS technology. PARTIAL RESET (PRS) MASTER RESET (MRS) ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating (2) V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.3V 0°C to +70°C; Industrial Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH t Clock Low Time ...

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... When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations reads are performed after a reset, IR will go HIGH after D writes to the FIFO 131,073 writes for the IDT72V295 and 262,145 writes for the IDT72V2105, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register ...

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... PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V295/72V2105 has internal registers for these offsets. Default set- tings are stated in the footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO in one of two ways; serial or parallel loading method ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 x 18 IDT72V295 (131,072 x 18-BIT EMPTY OFFSET (LSB) REGISTER DEFAULT VALUE 007FH LOW at Master Reset, 03FFH HIGH at Master Reset FULL OFFSET (LSB) REGISTER DEFAULT VALUE 007FH LOW at Master Reset, ...

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... words, should have been written into the FIFO and read from the FIFO between Reset (Master or Partial) and the time of Retransmit setup 131,072 for the IDT72V295 and D = 262,144 for the IDT72V2105. In FWFT mode 131,073 for the IDT72V295 and D = 262,145 for the IDT72V2105 ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read pointer is set to the first location of the RAM array. When OR goes LOW, Retransmit setup is complete; at the same time, the contents of the first location appear on the outputs ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 x 18 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS: MASTER RESET ( MRS ) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array ...

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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after after the valid WCLK cycle. D writes to the FIFO (D = 131,073 for the IDT72V295 and 262,145 for the IDT72V2105) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information. ...

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... In IDT Standard mode reads are performed after reset (MRS), PAF will go LOW after ( words are written to the FIFO. The PAF will go LOW after (131,072-m) writes for the IDT72V295 and (262,144-m) writes for the IDT72V2105. The offset “m” is the full offset value ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 x 18 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RSS t t RSS t t RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW LOW ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Figure 6. Partial Reset Timing 16 ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 WRITE WCLK 1 t (1) SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT REGISTER NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t 1 ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 18 ...

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... IDT72V295/72V2105 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 131,072 x 18, 262,144 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 19 ...

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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 131,072 for IDT72V295 and 262,144 for IDT72V2105. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. ...

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... There must be at least two words written to the FIFO before a Retransmit operation can be invoked. WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72V295 and for the IDT72V2105. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes ENS ...

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... PAF offset . maximum FIFO depth. In IDT Standard mode 131,072 for the IDT72V295 and 262,144 for the IDT72V2105. In FWFT mode 131,073 for the IDT72V295 and 262,145 for the IDT72V2105. is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t 3 ...

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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 131,072 for the IDT72V295 and 262,144 for the IDT72V2105. 2. For FWFT mode maximum FIFO depth 131,073 for the IDT72V295 and 262,145 for the IDT72V2105. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...

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... ANDing EF of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO, and separately ORing IR of every FIFO. Figure 23 demonstrates a width expansion using two IDT72V295/ 72V2105 devices. D and Q -Q from each device form a 36-bit wide output bus ...

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... FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO. Figure 24 shows a depth expansion using two IDT72V295/72V2105 de- vices. Care should be taken to select FWFT mode during Master Reset for all FIFOs in the depth expansion configuration. The first word written to an empty configuration will pass from one FIFO to the next (" ...

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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range is available as a standard device for 15ns. DATASHEET DOCUMENT HISTORY 9/12/2000 pg. 5. 12/18/2000 pgs and 26. 03/27/2001 pgs 6 and 26. ...