IDT72V2111 Integrated Device Technology, IDT72V2111 Datasheet
IDT72V2111
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IDT72V2111 Summary of contents
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... INPUT REGISTER RAM ARRAY 262,144 x 9 524,288 x 9 OUTPUT REGISTER IDT72V2101 IDT72V2111 LD SEN OFFSET REGISTER FF/IR PAF EF/OR FLAG PAE LOGIC HF FWFT/SI READ POINTER READ RT CONTROL LOGIC RCLK ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 DESCRIPTION (CONTINUED) The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 PAE and PAF can be programmed independently to switch at any point in memory. (See Table I and Table II.) Programmable offsets determine the flag switching ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write ...
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... Supply Voltage (Com'l & Ind'l) 0 Input High Voltage (Com'l & Ind'l) 2.0 Input Low Voltage (Com'l & Ind'l) — Operating Temperature Commercial 0 Operating Temperature Industrial -40 = -40°C to +85°C; JEDEC JESD8-A compliant) A IDT72V2101L IDT72V2111L (1) Commercial and Industrial t = 10, 15 CLK Min. Max. –1 1 –10 10 2.4 — ...
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... GND to 3.0V 3ns 1.5V 1.5V See Figure 2 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES = -40°C to +85°C; JEDEC JESD8-A compliant) A Com’l & Ind’l (1) Commercial IDT72V2101L15 IDT72V2101L20 IDT72V2111L15 IDT72V2111L20 Min. Max. Min. — 66.7 — — — — — ...
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... FIFO will cause the PAF to go LOW. Again reads are performed, the PAF will go LOW after (262,145-m) writes for the IDT72V2101 and (524,289-m) writes for the IDT72V2111, where m is the full offset value. The default setting for this value is stated in the footnote of Table 2. ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V2101/ 72V2111 has internal registers for these offsets. Default settings are stated in ...
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... FULL OFFSET (MSB) REGISTER DEFAULT 0H Figure 3. Offset Register Location and Default Values 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V2111 (524,288 x 9BIT) 7 EMPTY OFFSET (LSB) REGISTER DEFAULT VALUE 7FH LOW at Master Reset FFH HIGH at Master Reset 7 EMPTY OFFSET (MID-BYTE) REGISTER ...
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... WCLK edge Starting with Empty Offset (LSB) Ending with FUll Offset (MSB) No Operation Write Memory X X Read Memory Operation 10 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V2101 IDT72V2111 4669 drw 07 ...
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... SI input are written, one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. A total of 36 bits for the IDT72V2101 and 38 bits for the IDT72V2111. See Figure 13, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 When EF goes HIGH, Retransmit setup is complete and read operations may begin starting with the first location in memory. Since IDT Standard mode is selected, ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 9-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished ...
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... MRS or PRS), FF will go LOW after D writes the FIFO (D = 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111). See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the , including the first n relevant timing information. ...
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... PAF will go LOW after ( words are written to the FIFO. The PAF will go LOW after (262,144-m) writes for the IDT72V2101 and (524,288-m) writes for the IDT72V2111. The offset “m” is the full offset value. The default setting for this value is stated in the footnote of Table 1. ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS TM SUPERSYNC FIFO 262,144 x 9, 524,288 x 9 COMMERCIAL AND INDUSTRIAL 20 TEMPERATURE RANGES ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. ...
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... There must be at least two words written to the FIFO before a Retransmit operation can be invoked. WCLK t ENS SEN t LDS BIT 0 SI NOTE for the IDT72V2101 and for the IDT72V2111. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes ENS ...
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... PAF offset . maximum FIFO depth. In IDT Standard mode 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111. In FWFT mode 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111. is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t 3 ...
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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111. 2. For FWFT mode maximum FIFO depth 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...
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IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS SUPERSYNC FIFO TM 262,144 x 9, 524,288 x 9 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from ...
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... DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V2101 can easily be adapted to applications requiring depths greater than 262,144 and 524,288 for the IDT72V2111 with a 9-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 15ns is available as a standard device. DATASHEET DOCUMENT HISTORY 9/14/2000 pgs. 5. 12/18/2000 pgs and 27. 03/27/2001 pgs. 6 ...