IDT70V9089 Integrated Device Technology, IDT70V9089 Datasheet
IDT70V9089
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IDT70V9089 Summary of contents
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... High-speed clock to data access – Commercial: 6.5/7.5/9/12/15ns (max.) – Industrial: 9ns (max.) ◆ Low-power operation – IDT70V9089/79S Active: 429mW (typ.) Standby: 3.3mW (typ.) – IDT70V9089/79L Active: 429mW (typ.) Standby: 660mW (typ.) ◆ Flow-Through or Pipelined output mode on either port via ...
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... This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. Industrial and Commercial Temperature Ranges With an input data register, the IDT70V9089/79 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’ ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Pin Names Left Port Right Port CE CE Chip Enables , R/W R/W Read/Write Enable Output Enable L R (1) ( Address 0L 15L 0R 15R I/O - I/O I/O - I/O Data Input/Output CLK CLK Clock ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Recommended Operating Temperature and Supply Voltage Ambient Grade Temperature Commercial + Industrial - + NOTES: 1. This is the parameter T . This is the "instant on" case temperature. A Absolute Maximum Ratings Symbol Rating ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH NOTE < 2.0V input leakages are undefined. ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating CC L Current Outputs Disabled (Both Ports Active MAX CE and CE I Standby Current SB1 L (Both Ports - TTL ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 435Ω Figure 1. AC Output Test load. , tCD 1 tCD 2 (Typical, ns Figure 3. Typical Output Derating (Lumped Capacitive Load). ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol t Clock Cycle Time (Flow-Through) CYC1 (2) t Clock Cycle Time (Pipelined) CYC2 (2) t Clock High Time (Flow-Through) CH1 (2) t Clock Low Time (Flow-Through) ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol t Clock Cycle Time (Flow-Through) CYC1 t Clock Cycle Time (Pipelined) CYC2 t Clock High Time (Flow-Through) CH1 t Clock Low Time (Flow-Through) ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Timing Waveform of Read Cycle for Flow-Through Output (3,6) (FT/PIPE = "X" t CH1 CLK R (5) An ADDRESS t CD1 DATA OUT (1) t CKLZ (2) OE Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE ...
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... CE 0(B2 DATA OUT(B2) NOTES Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9089/79 for this waveform, and are setup for depth expansion in this example. ADDRESS 2. OE and ADS = V , R/W, CNTEN, and CNTRST = 1(B1) 1(B2) 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Timing Waveform Port-to-Port Flow-Through Read CLK "A" R/W "A" ADDRESS "A" MATCH DATA VALID IN "A" CLK "B" R/W "B" ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CL2 CLK R (4) An ADDRESS DATA IN (2) DATA OUT READ Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled) ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Timing Waveform of Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK R (4) An ADDRESS DATA IN t CD1 (2) Qn DATA OUT READ Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled) ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Timing Waveform of Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS t t SAD HAD ADS CNTEN (2) DATA OUT READ EXTERNAL ADDRESS Timing Waveform of Flow-Through Counter Read with ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS (3) (7) INTERNAL An ADDRESS t t SAD HAD ADS CNTEN DATA IN WRITE EXTERNAL ADDRESS ...
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... Depth and Width Expansion The IDT70V9089/79 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no require- ments for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. ...
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... Ordering Information A IDT XXXXX 99 A Device Power Speed Package Type Ordering Information for Flow-through Devices Old Flow-through Part Old Flow-through Part IDT Clock Solution for IDT70V9089/79 Dual-Port Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage I/O 70V9089/79 3.3 LVTTL A A Process/ Temperature Range Blank ...
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... IDT70V9089/79S/L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Datasheet Document History 1/18/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 14 Added Depth and Width Expansion section. 6/11/99: Page 3 Deleted note 6 for Table II 11/12/99: Replaced IDT logo ...