CAT28LV64 CATALYST [Catalyst Semiconductor], CAT28LV64 Datasheet

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CAT28LV64

Manufacturer Part Number
CAT28LV64
Description
64K-Bit CMOS PARALLEL E2PROM
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet

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© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Preliminary
CAT28LV64
64K-Bit CMOS PARALLEL E
DESCRIPTION
The CAT28LV64 is a low voltage, low power, CMOS
parallel E
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and V
additional timing and protection hardware. DATA Polling
and Toggle status bit signal the start and end of the self-
timed write cycle. Additionally, the CAT28LV64 features
hardware and software write protection.
BLOCK DIAGRAM
FEATURES
3.0V to 3.6 V Supply
Read Access Times:
– 250/300/350ns
Low Power CMOS Dissipation:
– Active: 8 mA Max.
– Standby: 100 A Max.
Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
Fast Write Cycle Time:
– 5ms Max.
Commercial, Industrial and Automotive
Temperature Ranges
A 5 –A 12
A 0 –A 4
V CC
WE
OE
CE
2
PROM organized as 8K x 8-bits. It requires a
CC
power up/down write protection eliminate
ADDR. BUFFER
ADDR. BUFFER
INADVERTENT
PROTECTION
TIMER
& LATCHES
CONTROL
& LATCHES
LOGIC
WRITE
2
PROM
DATA POLLING
1
HIGH VOLTAGE
TOGGLE BIT
GENERATOR
DECODER
The CAT28LV64 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
COLUMN
DECODER
AND
CMOS and TTL Compatible I/O
Automatic Page Write Operation:
– 1 to 32 Bytes in 5ms
– Page Load Timer
End of Write Detection:
– Toggle Bit
– DATA
Hardware and Software Write Protection
100,000 Program/Erase Cycles
100 Year Data Retention
ROW
DATA
DATA
DATA Polling
DATA
I/O BUFFERS
I/O 0 –I/O 7
8,192 x 8
E
ARRAY
2
PROM
32 BYTE PAGE
REGISTER
Doc. No. 25035-00 2/98
5094 FHD F02

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CAT28LV64 Summary of contents

Page 1

... Fast Write Cycle Time: – 5ms Max. Commercial, Industrial and Automotive Temperature Ranges DESCRIPTION The CAT28LV64 is a low voltage, low power, CMOS 2 parallel E PROM organized 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto- ...

Page 2

PIN CONFIGURATION DIP Package ( ...

Page 3

ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. – +125 C Storage Temperature ....................... – +150 C Voltage on Any Pin with (2) Respect to Ground ........... –2. with Respect to Ground ............... –2.0V ...

Page 4

D.C. OPERATING CHARACTERISTICS V = 3.0V to 3.6V, unless otherwise specified. cc Symbol Parameter I V Current (Operating, TTL ( Current (Standby, CMOS) SBC CC I Input Leakage Current LI I Output Leakage Current LO (3) ...

Page 5

Figure 1. A.C. Testing Input/Output Waveform INPUT PULSE LEVELS 0.0 V Figure 2. A.C. Testing Load Circuit (example) A.C. CHARACTERISTICS, Write Cycle V = 3.0V to 3.6V, unless otherwise specified. cc Symbol Parameter t Write ...

Page 6

... DEVICE OPERATION Read Data stored in the CAT28LV64 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either goes high. This 2-line control architec- ture can be used to eliminate bus contention in a system environment ...

Page 7

... Page Write The page write mode of the CAT28LV64 (essentially an extended BYTE WRITE mode) allows from bytes of data to be programmed within a single E cycle. This effectively reduces the byte-write time by a factor of 32. Following an initial WRITE operation (WE pulsed low, for t , and then high) the page write mode can begin by ...

Page 8

DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O are ...

Page 9

... AC charac- INIT performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28LV64 is in the standard operating mode). Figure 10. Write Sequence for Deactivating (1) 28LV64 F12 ...

Page 10

... Product Number * -40˚C to +125˚C is available upon request Notes: (1) The device used in the above example is a CAT28LV64NI-25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel). Doc. No. 25035-00 2/98 To allow the user the ability to program the device with PROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection ...

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