74lvth16543 Fairchild Semiconductor, 74lvth16543 Datasheet
74lvth16543
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74lvth16543 Summary of contents
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... Features Input and output interface capability to systems Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16543) Also available without bushold feature (74LVT16543) Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free bus loading Outputs source/sink 32 mA ...
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Connection Diagram Functional Description The LVT16543 and LVTH16543 contain two sets of D-type latches, with separate input and output controls for each. For data flow from for example, the Enable (CEAB) input must be ...
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Logic Diagrams Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Please note that this diagram is provided only for the understanding of logic operations and ...
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Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Supply Current ...
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... Increase in Power Supply Current CC (Note 6) Note 3: Applies to bushold versions only (74LVTH16543) Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than V ...
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AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH t Data to Outputs PHL t Propagation Delay PLH PHL t Output Enable Time PZH PZL t Output Disable ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...