74lv259 NXP Semiconductors, 74lv259 Datasheet

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74lv259

Manufacturer Part Number
74lv259
Description
8-bit Addressable Latch
Manufacturer
NXP Semiconductors
Datasheet
1. General description
2. Features
The 74LV259 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC259 and 74HCT259. The 74LV259 is a high-speed 8-bit addressable latch
designed for general purpose storage applications in digital systems. The 74LV259 is
multifunctional device capable of storing single-line data in eight addressable latches, and
also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are
available. The 74LV259 also incorporates an active LOW common reset (MR) for resetting
all latches, as well as, an active LOW enable input (LE).
The 74LV259 has four modes of operation as shown in the mode select table. In the
addressable latch mode, data on the data line (D) is written into the addressed latch. The
addressed latch will follow the data input with all non-addressed latches remaining in their
previous states. In the memory mode, all latches remain in their previous states and are
unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode,
the addressed output follows the state of the (D) input with all other outputs in the LOW
state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2)
and data (D) input. When operating the 74LV259 as an address latch, changing more than
one bit of address could impose a transient-wrong address. Therefore, this should only be
done while in the memory mode.
74LV259
8-bit addressable latch
Rev. 03 — 2 January 2008
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
Typical output ground bounce < 0.8 V at V
Typical HIGH-level output voltage (V
T
Combines demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
amb
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
= 25 C
CC
OH
) undershoot: > 2 V at V
= 2.7 V and V
CC
= 3.3 V and T
CC
= 3.6 V
amb
= 25 C
CC
Product data sheet
= 3.3 V and

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74lv259 Summary of contents

Page 1

... The 74LV259 also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW enable input (LE). The 74LV259 has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states ...

Page 2

... 001aah118 Fig 1. Logic symbol 74LV259_3 Product data sheet Description DIP16 plastic dual in-line package; 16 leads (300 mil) SO16 plastic small outline package; 16 leads; body width 3.9 mm SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm TSSOP16 plastic thin shrink small outline package; 16 leads; ...

Page 3

... V) latch output Rev. 03 — 2 January 2008 74LV259 8-bit addressable latch 001aah120 74LV259 terminal 1 index area ( ...

Page 4

... Rev. 03 — 2 January 2008 74LV259 8-bit addressable latch Mode addressable latch memory active HIGH 8-channel demultiplexer reset ...

Page 5

... DIP16 package SO16 package (T)SSOP16 package DHVQFN16 package Conditions 5.5 V, but LV devices are guaranteed to function down Rev. 03 — 2 January 2008 74LV259 8-bit addressable latch Min 0.5 [ [ [2] - [3] - [4] - [5] - ...

Page 6

... 5 GND 5 per input amb Rev. 03 — 2 January 2008 74LV259 8-bit addressable latch + +125 C Unit [1] Min Typ Max Min 0 0.9 1 1 ...

Page 7

... NXP B.V. 2008. All rights reserved. 74LV259 Unit Max - ...

Page 8

... +125 C [1] Min Typ Max Min - © NXP B.V. 2008. All rights reserved. 74LV259 Unit Max - ...

Page 9

... An input V M GND t PHL output Table input V M GND t PHL output Table 9. Rev. 03 — 2 January 2008 74LV259 8-bit addressable latch t PLH 001aah121 t PLH 001aah122 t PLH 001aah123 © NXP B.V. 2008. All rights reserved ...

Page 10

... GND Table ADDRESS STABLE M GND GND Table 9. Rev. 03 — 2 January 2008 74LV259 8-bit addressable latch 001aah124 001aah125 t h 001aah126 © NXP B.V. 2008. All rights reserved ...

Page 11

... CC 2 3.6 V 2.7 V 74LV259_3 Product data sheet Input V M 0. PULSE D.U.T. GENERATOR Rev. 03 — 2 January 2008 74LV259 8-bit addressable latch Output V M 0. 001aaa663 of the pulse generator 2.5 ns 2.5 ns © NXP B.V. 2008. All rights reserved. ...

Page 12

... REFERENCES JEDEC JEITA Rev. 03 — 2 January 2008 8-bit addressable latch ( 6.48 3.60 8.25 2.54 7.62 6.20 3.05 7.80 0.26 0.14 0.32 0.1 0.3 0.24 0.12 0.31 EUROPEAN PROJECTION 74LV259 SOT38-4 ( max. 10.0 0.254 0.76 8.3 0.39 0.01 0.03 0.33 ISSUE DATE 95-01-14 03-02-13 © NXP B.V. 2008. All rights reserved ...

Page 13

... detail 6.2 1.0 0.7 1.05 0.25 0.25 5.8 0.4 0.6 0.039 0.028 0.041 0.01 0.01 0.016 0.020 EUROPEAN PROJECTION 74LV259 SOT109 ( 0.7 0 0.028 0.004 0.012 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2008. All rights reserved ...

Page 14

... JEDEC JEITA MO-150 Rev. 03 — 2 January 2008 8-bit addressable latch detail 1.03 0.9 0.2 0.13 1.25 0.63 0.7 EUROPEAN PROJECTION 74LV259 SOT338 ( 1.00 8 0.1 o 0.55 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2008. All rights reserved ...

Page 15

... MO-153 Rev. 03 — 2 January 2008 8-bit addressable latch detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION 74LV259 SOT403 ( 0.40 8 0.1 o 0.06 0 ISSUE DATE 99-12-27 03-02-18 © NXP B.V. 2008. All rights reserved ...

Page 16

... 3.6 2.15 2.6 1.15 0.5 2.5 3.4 1.85 2.4 0.85 REFERENCES JEDEC JEITA MO-241 - - - Rev. 03 — 2 January 2008 8-bit addressable latch detail 0.5 0.05 0.1 0.1 0.05 0.3 EUROPEAN PROJECTION 74LV259 SOT763 ISSUE DATE 02-10-17 03-01-27 © NXP B.V. 2008. All rights reserved ...

Page 17

... DHVQFN16 package added. 7: derating values added for DHVQFN16 package. 12: outline drawing added for DHVQFN16 package. Product specification Product specification Rev. 03 — 2 January 2008 74LV259 8-bit addressable latch Change notice Supersedes - 74LV259_2 - 74LV259_1 - - © NXP B.V. 2008. All rights reserved ...

Page 18

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 2 January 2008 74LV259 8-bit addressable latch © NXP B.V. 2008. All rights reserved ...

Page 19

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LV259 All rights reserved. Date of release: 2 January 2008 Document identifier: 74LV259_3 ...

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